BV52A Search Results

BV52A Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY2SSTU877 Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 Text: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).	Original	CY2SSTU877 500-MHz, 10-Output CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32	PDF
K 2925 Abstract: F1E6 Text: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features ential pair of clock outputs Y[0:9], Y#[0:9] and one differential pair of feedback clock outputs (FBOUT, FBOUT#). • Operating frequency: 125 MHz to 500 MHz The input clocks (CK, CK#), the feedback clocks (FBIN,	Original	CY2SSTU877 500-MHz, 10-Output 52-ball CY2SSTU877 K 2925 F1E6	PDF
DDR533 Abstract: CY2SSTU877BVXI-32 CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T Text: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).	Original	CY2SSTU877 10-Output CY2SSTU877 DDR533 CY2SSTU877BVXI-32 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T	PDF
CY2SSTU877 Abstract: CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin Text: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).	Original	CY2SSTU877 500-MHz, 10-Output CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 lz 40 6 pin	PDF
ddr5 Abstract: DDR533 BV52A CY2SSTU877 CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball Text: CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair CK, CK# to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#).	Original	CY2SSTU877 10-Output CY2SSTU877 ddr5 DDR533 BV52A CY2SSTU877BVXC-32 CY2SSTU877BVXC-32T CY2SSTU877BVXI-32 DDR-533 DDRII 52-ball	PDF
JEDEC MO 224 Abstract: CY2SSTU877 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape Text: CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter cycle-to-cycle : < 40 ps	Original	CY2SSTU877 500-MHz, 10-Output 52-ball 40-pin CY2SSTU877 JEDEC MO 224 CY2SSTU877BVC-XX CY2SSTU877BVI-XX CY2SSTU877BVI-XXT CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877LFI-XX JEDEC pin1 qfn tape	PDF