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    MT4C4007JDJ-7

    Abstract: MT4C4007JDJ7 marking 3GY MRP21
    Text: PRELIMINARY iimiy—a n i v f wlt4C40Q7J S t MEG x: 4 DRAM 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL SELF REFRESH ] MATURES • Single +5V ±10% pow er supply ■ JED EC-standard pinout and packages ■ High-performance C M O S silicon-gate process


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    PDF wlt4C40Q7J 024-cycle 128ms 25-35ns 20/26-Pin MT4C4007J C1995. MT4C4007JDJ-7 MT4C4007JDJ7 marking 3GY MRP21