W25Z040A Search Results

M17S

Abstract: No abstract text available
Text: W25Z040A 128K x 36 PIPELINED ZWS SRAM GENERAL DESCRIPTION The W 25Z040A is a high-speed, low-power, Zero-Wait-State ZWS Synchronous Pipelined CMOS Static RAM organized as 131,072 x 36 bits. A built-in two-bit burst address counter supports both Linear and Interleaved burst mode. The mode to be executed is controlled by the LBO pin. A snooze