M17S
Abstract: No abstract text available
Text: 25Z040A 128K x 36 PIPELINED ZWS SRAM GENERAL DESCRIPTION The W 25Z040A is a high-speed, low-power, Zero-Wait-State ZWS Synchronous Pipelined CMOS Static RAM organized as 131,072 x 36 bits. A built-in two-bit burst address counter supports both Linear and Interleaved burst mode. The mode to be executed is controlled by the LBO pin. A snooze
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W25Z040A
25Z040A
fjfr-94SSS?
i8-5-M17S
8S2-275S2G
SSS-2-27'
M17S
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