VSSOP8
Abstract: NAIS Relay 5v DR PVSP0008KA-A
Text: RENESAS Code PVSP0008KA-A Previous Code TTP-8DB/TTP-8DBV MASS[Typ.] 0.010g D F 1.5 ±0.2 8 5 bp c HE E c1 b1 Terminal cross section 1 L1 4 A2 bp A1 e 0.17 JEITA Package Code P-VSSOP8-2.3x2-0.50 Detail F Reference Symbol Dimension in Millimeters Min Nom Max
|
Original
|
PDF
|
PVSP0008KA-A
VSSOP8
NAIS Relay 5v DR
PVSP0008KA-A
|
Untitled
Abstract: No abstract text available
Text: Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index A3 θ Lp 1 4 e L detail X w M bp 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT
|
Original
|
PDF
|
OT765-1
MO-187
|
VSSOP8
Abstract: JEDEC MO-187 MO-187 VSSOP-8 SOT765-1 sot765
Text: PDF: 2002 Jun 07 Philips Semiconductors Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index A3 θ Lp 1 4 e L detail X w M bp 2.5 5 mm scale DIMENSIONS (mm are the original dimensions)
|
Original
|
PDF
|
OT765-1
MO-187
VSSOP8
JEDEC MO-187
MO-187
VSSOP-8
SOT765-1
sot765
|
VSSOP8
Abstract: No abstract text available
Text: P8 SO VS SOT765-1 VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code 12NC ending 125 Rev. 5 — 3 May 2013 Packing information 1. Packing method Printed plano box Barcode label Reel
|
Original
|
PDF
|
OT765-1
001aak603
prod715
OT765-1
VSSOP8
|
nz104
Abstract: No abstract text available
Text: 74LVC2G66 Bilateral switch Rev. 7 — 22 June 2012 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).
|
Original
|
PDF
|
74LVC2G66
74LVC2G66
nz104
|
MARKING V7 6-PIN
Abstract: No abstract text available
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
|
Original
|
PDF
|
74LVC3G14
74LVC3G14
MARKING V7 6-PIN
|
Marking code V7
Abstract: No abstract text available
Text: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
|
Original
|
PDF
|
74LVC2G00
74LVC2G00
Marking code V7
|
T4531
Abstract: No abstract text available
Text: THS4531 www.ti.com SLOS358B – SEPTEMBER 2011 – REVISED MARCH 2012 Ultra Low Power, Rail-to-Rail Output, Fully-Differential Amplifier Check for Samples: THS4531 FEATURES DESCRIPTION • The THS4531 is a low-power, fully-differential op amp with input common-mode range below the negative
|
Original
|
PDF
|
THS4531
SLOS358B
THS4531
T4531
|
74AHC3GU04
Abstract: 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM JESD22-A114E MO-187
Text: 74AHC3GU04 Inverter Rev. 03 — 26 January 2009 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the inverting single stage function. 2. Features • Symmetrical output impedance ■ High noise immunity
|
Original
|
PDF
|
74AHC3GU04
74AHC3GU04
JESD22-A114E
JESD22-A115-A
JESD22-C101C
74AHC3GU04DP
74AHC3GU04DC
74AHC3GU04DP
74AHC3GU04GM
MO-187
|
74AHC2G08
Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
Text: 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 03 — 12 January 2009 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features • Symmetrical output impedance
|
Original
|
PDF
|
74AHC2G08;
74AHCT2G08
74AHCT2G08
JESD22-A114E
JESD22-A115-A
JESD22-C101C
74AHC2G08DP
74AHC2G08
74AHC2G08DC
74AHC2G08DP
74AHCT2G08DC
74AHCT2G08DP
|
74LVC1G53
Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
Text: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select
|
Original
|
PDF
|
74LVC1G53
74LVC1G53
74LVC1G53DC
74LVC1G53DP
74LVC1G53GD
74LVC1G53GT
JESD22-A114E
MO-187
V53 TSSOP8
|
74HC3G04DP
Abstract: 74HC3G04 74HC3G04DC 74HC3G04GD 74HCT3G04 74HCT3G04DC 74HCT3G04DP 74HCT3G04GD JESD22-A114E
Text: 74HC3G04; 74HCT3G04 Inverter Rev. 03 — 2 July 2008 Product data sheet 1. General description The 74HC3G04 and 74HCT3G04 are high-speed Si-gate CMOS devices. They provide three inverting buffers. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
|
Original
|
PDF
|
74HC3G04;
74HCT3G04
74HC3G04
74HCT3G04
JESD22-A114E
JESD22-A115-A
HCT3G04
74HC3G04DP
74HC3G04DC
74HC3G04GD
74HCT3G04DC
74HCT3G04DP
74HCT3G04GD
|
74AUP2G125
Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
Text: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 05 — 2 February 2009 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE
|
Original
|
PDF
|
74AUP2G125
74AUP2G125
74AUP2G125DC
74AUP2G125GT
JESD22-A114E
JESD78
|
74LVC3G14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
|
Original
|
PDF
|
74LVC3G14
74LVC3G14
74LVC3G14DC
74LVC3G14DP
74LVC3G14GM
74LVC3G14GT
JESD22-A114E
MO-187
|
|
|
VSSOP8
Abstract: 74HC3GU04 74HC3GU04DC 74HC3GU04DP JESD22-A114E MO-187
Text: 74HC3GU04 Inverter Rev. 03 — 11 May 2009 Product data sheet 1. General description The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V.
|
Original
|
PDF
|
74HC3GU04
74HC3GU04
JESD22-A114E
JESD22-A115-A
VSSOP8
74HC3GU04DC
74HC3GU04DP
MO-187
|
74AVCH2T45
Abstract: 74AVCH2T45DC 74AVCH2T45GT JESD22-A114E
Text: 74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 03 — 6 May 2009 Product data sheet 1. General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports nA and nB , a direction control input
|
Original
|
PDF
|
74AVCH2T45
74AVCH2T45
74AVCH2T45DC
74AVCH2T45GT
JESD22-A114E
|
74AHC3G04
Abstract: 74AHC3G04DC 74AHC3G04DP 74AHCT3G04 74AHCT3G04DC 74AHCT3G04DP JESD22-A114E
Text: 74AHC3G04; 74AHCT3G04 Inverter Rev. 02 — 26 January 2009 Product data sheet 1. General description The 74AHC3G04; 74AHCT3G04 is a high-speed Si-gate CMOS device. The 74AHC3G04; 74AHCT3G04 provides three inverting buffers. 2. Features • Symmetrical output impedance
|
Original
|
PDF
|
74AHC3G04;
74AHCT3G04
74AHCT3G04
JESD22-A114E
JESD22-A115-A
JESD22-C101C
74AHC3G04DP
74AHC3G04
74AHC3G04DC
74AHC3G04DP
74AHCT3G04DC
74AHCT3G04DP
|
74LVC2G66
Abstract: 74LVC2G66DC 74LVC2G66DP 74LVC2G66GT 74LVCV2G66 JESD22-A114E JESD78
Text: 74LVC2G66 Bilateral switch Rev. 04 — 1 July 2008 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).
|
Original
|
PDF
|
74LVC2G66
74LVC2G66
74LVC2G66DC
74LVC2G66DP
74LVC2G66GT
74LVCV2G66
JESD22-A114E
JESD78
|
74LVC2G126
Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187
Text: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 08 — 5 May 2008 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE
|
Original
|
PDF
|
74LVC2G126
74LVC2G126
74LVC2G126DC
74LVC2G126DP
74LVC2G126GD
74LVC2G126GM
74LVC2G126GT
JESD22-A114E
MO-187
|
74AUP2G240
Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78
Text: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE
|
Original
|
PDF
|
74AUP2G240
74AUP2G240
74AUP2G240DC
74AUP2G240GT
JESD22-A114E
JESD78
|
74HC
Abstract: 74HC2G66 74HC2G66DC 74HC2G66DP 74HCT2G66 74HCT2G66DC 74HCT2G66DP JESD22-A114E
Text: 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Rev. 05 — 26 January 2009 Product data sheet 1. General description 74HC2G66 and 74HCT2G66 are high-speed Si-gate CMOS devices. They are dual single-pole single-throw analog switches. Each switch has two input/output pins
|
Original
|
PDF
|
74HC2G66;
74HCT2G66
74HC2G66
74HCT2G66
74HC2G66
JESD22-A114E
HCT2G66
74HC
74HC2G66DC
74HC2G66DP
74HCT2G66DC
74HCT2G66DP
|
74LVC2G241
Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E
Text: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 09 — 10 June 2008 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE:
|
Original
|
PDF
|
74LVC2G241
74LVC2G241
74LVC2G241DC
74LVC2G241DP
74LVC2G241GD
74LVC2G241GM
74LVC2G241GT
JESD22-A114E
|
74LVCV2G66
Abstract: 74LVCV2G66DC 74LVCV2G66DP MO-187
Text: 74LVCV2G66 Overvoltage tolerant bilateral switch Rev. 02 — 3 July 2008 Product data sheet 1. General description The 74LVCV2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVCV2G66 provides two single pole single throw analog or digital switches. Each
|
Original
|
PDF
|
74LVCV2G66
74LVCV2G66
74LVCV2G66DC
74LVCV2G66DP
MO-187
|
Untitled
Abstract: No abstract text available
Text: ADC081C021, ADC081C027 www.ti.com SNAS447B – FEBRUARY 2008 – REVISED FEBRUARY 2009 ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter with Alert Function Check for Samples: ADC081C021, ADC081C027 FEATURES 1 • 23 • • • • •
|
Original
|
PDF
|
ADC081C021,
ADC081C027
SNAS447B
ADC081C021/ADC081C027
100kHz)
400kHz)
|
