verilog code for 64 32 bit register
Abstract: verilog code for 8 bit shift register verilog code for 8 bit fifo register vhdl code for 8 bit shift register vhdl code for 8 bit register vhdl code for shift register using d flipflop vhdl code for 4 bit shift register SRLC64E SRLC32E VHDL of 4-BIT LEFT SHIFT REGISTER
Text: R Look-Up Tables as Shift Registers SRLUTs Verilog Template // // Module: SelectRAM_16S // // Description: Verilog instantiation template // Distributed SelectRAM // Single Port 16 x 1 // can be used also for RAM16X1S_1 // // Device: Virtex-II Pro Family
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RAM16X1S
h0000;
RAM16X1S
SRLC16E
SRLC16E
UG012
verilog code for 64 32 bit register
verilog code for 8 bit shift register
verilog code for 8 bit fifo register
vhdl code for 8 bit shift register
vhdl code for 8 bit register
vhdl code for shift register using d flipflop
vhdl code for 4 bit shift register
SRLC64E
SRLC32E
VHDL of 4-BIT LEFT SHIFT REGISTER
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verilog code for implementation of des
Abstract: APA150-STD RT54SX-S verilog code for des wireless encrypt vhdl code for DES algorithm
Text: v3.0 Core3DES P ro d u ct S u m m a r y • RTL Version I n t en d ed U se – Verilog or VHDL Core Source Code – Core Synthesis Scripts • Actel-Developed Testbench Verilog and VHDL • Whenever Data is Transmitted Across an Accessible Medium (wires, wireless, etc.)
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168-bit
56-bit
verilog code for implementation of des
APA150-STD
RT54SX-S
verilog code for des
wireless encrypt
vhdl code for DES algorithm
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MCM69C232
Abstract: MPC860SAR
Text: Order this document by ANxxxx/D Microprocessor and Memory Technologies Group ANxxxx Application Note MPC860SAR Microprocessor ATM CAM Interface Application V1.0 - Initial release V1.1 - August 5, 1998 - Fixed bugs found during Verilog verification: 1 changed match port logic for MS to
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MPC860SAR
MCM69C232
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AN2060
Abstract: MCM69C232 MPC860SAR
Text: Freescale Semiconductor Order this document by AN2060/D AN2060 Application Note MPC860SAR Microprocessor ATM CAM Interface Application Freescale Semiconductor, Inc. V1.0 - Initial release V1.1 - August 5, 1998 - Fixed bugs found during Verilog verification: 1 changed match port logic for MS to
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AN2060/D
AN2060
MPC860SAR
AN2060
MCM69C232
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Untitled
Abstract: No abstract text available
Text: Standard Products UT6325 RadTol Eclipse FPGA Data Sheet September 2008 www.aeroflex.com/FPGA Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI
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UT6325
16-bit
MIL-STD-883
120MeV-cm2/mg
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UT6325
Abstract: Diode smd f6 pioneer a9 CLGA484 smd diode h15 SMD H21 smd M21 smd marking g8 smd w20 smd transistor M21
Text: Standard Products UT6325 RadTol Eclipse FPGA Data Sheeet March 2010 www.aeroflex.com/FPGA Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI
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UT6325
208-pin
16-bit
Diode smd f6
pioneer a9
CLGA484
smd diode h15
SMD H21
smd M21
smd marking g8
smd w20
smd transistor M21
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Untitled
Abstract: No abstract text available
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet July 2005 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
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Untitled
Abstract: No abstract text available
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet June 2006 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
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smd M16
Abstract: smd marking w6 208-Pin CQFP 5962-0422 marking SMD Y12 SMD capacitor aa4 aa5
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet June 16, 2006 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
smd M16
smd marking w6
208-Pin CQFP
5962-0422
marking SMD Y12
SMD capacitor aa4 aa5
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packet
Abstract: 75K72100 verilog code for communication between fpga 75K62100 75P42100 75P52100 verilog cam
Text: VERILOG PACKET INTERFACE Product MODULE TO INTERFACE IDT Brief HIGH PERFORMANCE NSE TO 75HKD0X2100A01 ALTERA FPGA Introduction Background IDT provides proven, industry-leading network search engines NSEs and a comprehensive suite of software that enable and accelerate
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75HKD0X2100A01
6463d01
packet
75K72100
verilog code for communication between fpga
75K62100
75P42100
75P52100
verilog cam
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CAM circuit diagram
Abstract: Content Addressable Memory AN2060 MCM69C232 MPC860SAR ATM machine using microprocessor 4Kx64 9A26
Text: Freescale Semiconductor, Inc. Order this document by AN2060/D AN2060 Application Note MPC860SAR Microprocessor ATM CAM Interface Application Freescale Semiconductor, Inc. V1.0 - Initial release V1.1 - August 5, 1998 - Fixed bugs found during Verilog verification: 1 changed match port logic for MS to
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AN2060/D
AN2060
MPC860SAR
CAM circuit diagram
Content Addressable Memory
AN2060
MCM69C232
ATM machine using microprocessor
4Kx64
9A26
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w18 SMD
Abstract: No abstract text available
Text: Standard Products UT6325 RadHard Eclipse FPGA Data Sheet September 2006 www.aeroflex.com/RadHardFPGA Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI
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UT6325
16-bit
MIL-STD-883
120MeV-cm2/min
w18 SMD
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CCGA484
Abstract: No abstract text available
Text: Standard Products UT6325 RadHard Eclipse FPGA Data Sheet May 2007 www.aeroflex.com/RadHardFPGA Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI
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UT6325
16-bit
MIL-STD-883
120MeV-cm2/mg
CCGA484
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PDF
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Untitled
Abstract: No abstract text available
Text: Standard Products UT6325 RadHard Eclipse FPGA Data Sheet December 2007 www.aeroflex.com/RadHardFPGA Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI
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UT6325
16-bit
MIL-STD-883
120MeV-cm2/mg
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208-Pin CQFP
Abstract: CLGA smd M16
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Data Sheet August 22, 2006 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
208-Pin CQFP
CLGA
smd M16
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CDR33 Reliability data
Abstract: No abstract text available
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet December, 2004 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
CDR33 Reliability data
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ceramic pin grid array package plating
Abstract: No abstract text available
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet May, 2005 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
ceramic pin grid array package plating
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UT200SpW01
Abstract: synchronous dual port ram 16*8 verilog code EL B17
Text: Standard Products RadHard Eclipse FPGA Family with Embedded SpaceWire Advanced Data Sheet August 29, 2006 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
UT200SpW01
synchronous dual port ram 16*8 verilog code
EL B17
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75K72100
Abstract: packet 75K62100 75P42100 75P52100 IDT75HKD0X2100X01
Text: VERILOG PACKET INTERFACE MODULE TO INTERFACE IDT HIGH PERFORMANCE NSE TO XILINX FPGA Product Brief 75HKD0X2100X01 Introduction Background IDT provides proven, industry-leading network search engines NSEs and a comprehensive suite of software that enable and accelerate
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75HKD0X2100X01
6459d01
75K72100
packet
75K62100
75P42100
75P52100
IDT75HKD0X2100X01
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stopwatch vhdl
Abstract: verilog code for stop watch led watch module VHDL code of lcd display led watch module vhdl code for Clock divider for FPGA lcd module verilog verilog code to generate square wave verilog code lcd vhdl code 7 segment display fpga Xilinx lcd
Text: Chapter 1 Synopsys Design Compiler/FPGA Compiler/ ModelSim Tutorial for CPLDs This tutorial shows you how to use Synopsys’ Design Compiler/ FPGA Compiler VHDL/Verilog for compiling XC9500/XL/XV and Xilinx CoolRunner (XCR) CPLD designs, and Model Technology’s
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XC9500/XL/XV
XC9500"
stopwatch vhdl
verilog code for stop watch
led watch module
VHDL code of lcd display led watch module
vhdl code for Clock divider for FPGA
lcd module verilog
verilog code to generate square wave
verilog code lcd
vhdl code 7 segment display fpga
Xilinx lcd
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smd marking g8
Abstract: No abstract text available
Text: Standard Products RadHard Eclipse FPGA Family 6250 and 6325 Advanced Data Sheet June 16, 2006 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM
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16-bit
MIL-STD-883
120MeV-cm2/mg
smd marking g8
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RTAX2000
Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
Text: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators
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32-Bit
64-Bit
RTAX2000
ProASIC3 A3P250
RTAX1000S
A3P125
A54SX16A
A54SX32A
APA075
AX125
PAR64
RTAX250S
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SHA-512
Abstract: verilog code for sha1 hash function FIPS-180-2 SHA-1 using vhdl FIPS180-2 SHA-384 SHA-256 xilinx spartan 3 XC3S2000 xilinx vhdl code for digital clock SHA equivalent
Text: SHA-384, SHA-512 Hashing, Fast Helion May 15, 2007 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide Design File Formats Xilinx netlist; VHDL or Verilog source Helion Technology Limited code also available Ash House, Breckenwood Road,
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SHA-384,
SHA-512
SHA-384
SHA-512,
/fips/fips180-2/fips180-2withchangenotice
SHA-512
verilog code for sha1 hash function
FIPS-180-2
SHA-1 using vhdl
FIPS180-2
SHA-256
xilinx spartan 3 XC3S2000
xilinx vhdl code for digital clock
SHA equivalent
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vhdl code for powerpc
Abstract: EP100 MPC8260 XCV400E-FG676
Text: EP100 PowerPC Bus Slave April 15, 2003 Product Specification AllianceCORE Facts Core Specifics See Table 1. Provided with Core Eureka Technology, Inc. Documentation User guide Design File Formats EDIF netlist Constraints File Top201.ucf Verification VHDL or Verilog test bench
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EP100
Top201
vhdl code for powerpc
MPC8260
XCV400E-FG676
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