IDT77V1264L200
Abstract: No abstract text available
Text: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for
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IDT77V1264L200
af-phy-040
77V1254L25
77V1264L200
IDT77V1264L200
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SA1381
Abstract: SS823 RDATA13 3RA61 AC21T n25h VSS1490 bwd9 HAD44 HAD48
Text: A B C D REVISIONS ZONE LTR CN8237/CX29704 PCB:BT01-D255-011 A DESCRIPTION INITIAL APPROVED DATE RELEASE 1 1 DL1 DELAYLINE 2.5NS 1 2 U7 3 CN8237 SEGMENTATION SCLK0 R124 18 DL2 B3SCLK0 A3SCLK1 R116 18 DELAYLINE 2.5NS POWER VDD PINS E7, E8, E11, E12, E15, E16
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CN8237/CX29704
BT01-D255-011
CN8237
BT01-X250
SA1381
SS823
RDATA13
3RA61
AC21T
n25h
VSS1490
bwd9
HAD44
HAD48
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ht12 decoder
Abstract: 417-183 epd driver ic nec CB-11
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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d88-6130
ht12 decoder
417-183
epd driver ic
nec CB-11
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93CS56L
Abstract: con20a 34.368Mhz oscillator TXDATA15 13k g4 TXDATA13 LA10 LA12 GPIO03 LA-1105
Text: 1 2 3 C15 0.1uF AD1 AD5 AD3 AD8 AD7 AD12 AD10 -CBE1 AD14 -SERR -LOCK -PERR CON1 1 CON1 J5 1 CON1 J4 1 CON1 J3 1 J2 -DEVSEL -IRDY AD17 -CBE2 AD21 AD19 -CBE3 AD23 AD27 AD25 AD31 AD29 CLK A C16 0.1uF C17 0.1uF C12 0.1uF VIO VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3
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93CS56L
TxData10
TxData11
TxData12
TxData13
TxData14
TxData15
RxData10
RxData11
RxData12
93CS56L
con20a
34.368Mhz oscillator
TXDATA15
13k g4
TXDATA13
LA10
LA12
GPIO03
LA-1105
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ATM25
Abstract: IDT77V1264L200 ST6200T
Text: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for
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IDT77V1264L200
af-phy-040
77V1254L25
144-Pin
PU-144)
77V1264L200
77V1254
25Mb/s
ATM25
IDT77V1264L200
ST6200T
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RX 433
Abstract: No abstract text available
Text: IDT77V1254L25 Quad Port PHY Physical Layer for 25.6 and 51.2 ATM Networks Features List ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels
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IDT77V1254L25
IDT77V1254L25
77V1254L25-to-ATM
16-bit
RX 433
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I960CA
Abstract: CN8236 CX28250EVM Bt8223
Text: CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface with service-specific functions in a single package for AAL0, 3/4, and 5 operations.
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CN8236
CN8236
28236-DSH-001-B
I960CA
CX28250EVM
Bt8223
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ic 313
Abstract: S3043 S3044
Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD98414 2.4 Gbps ATM SONET FRAMER The µPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer
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PD98414
NEASCOT-P70)
STS-48c/SDH
STM-16c
ic 313
S3043
S3044
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HTD12
Abstract: 45x45 bga CBD62 cba8 373 ic HTD24 application of microprocessor in aircrafts 6-pin plastic A6 tray 45x45 CBD43
Text: DATA SHEET MOS INTEGRATED CIRCUIT PD98410 1.2G ATM SWITCH LSI DESCRIPTION The PD98410 NEASCOT-X10TM is an LSI integrating ATM switch functions on a single chip. It has four UTOPIA level2 interfaces and can switch 24 24 circuits by using a multi-PHY connection. This LSI also realizes a switching
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PD98410
NEASCOT-X10TM)
bits/40
16Kial:
HTD12
45x45 bga
CBD62
cba8
373 ic
HTD24
application of microprocessor in aircrafts
6-pin plastic A6
tray 45x45
CBD43
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t04 68 3 pin transistor
Abstract: MD 202 flame relay AC03 nec alps lcd 14 pin t04 68 3 pin diode transistor z5t S3043 S3044 STM-16 z046
Text: User’s Manual µPD98414 NEASCOT-P70TM ATM 2.4Gbps SONET Framer Document No. S14166EJ4V0UM00 (4th edition) Date Published December 2001 J CP(K) 1999 1991 Printed in Japan [MEMO] 2 User's Manual S14166EJ4V0UM SUMMARY OF CONTENTS CHAPTER 1 GENERAL .13
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PD98414
NEASCOT-P70TM)
S14166EJ4V0UM00
S14166EJ4V0UM
t04 68 3 pin transistor
MD 202 flame relay
AC03 nec
alps lcd 14 pin
t04 68 3 pin diode
transistor z5t
S3043
S3044
STM-16
z046
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8032 Intel Microprocessor data Sheet
Abstract: atm header error checking ATM machine using microcontroller dmo 265 NAIS 210 T7296 3-bit comparator circuit receives two 3-bit 8052 microcontroller Intel LOG RX 2 1018 IC ordinary calculator programming
Text: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public
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XRT7245
XRT7245
CellOf52Bytes)
8032 Intel Microprocessor data Sheet
atm header error checking
ATM machine using microcontroller
dmo 265
NAIS 210
T7296
3-bit comparator circuit receives two 3-bit
8052 microcontroller Intel
LOG RX 2 1018 IC
ordinary calculator programming
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DSLAM configuration AWS
Abstract: rx bc nbk TSC 13003 pcr 465 ATML 18751 circuit BKC International mpc82 bsdl nd1 marking code acm 33221
Text: MC92520 ATM Cell Processor User’s Manual MC92520UM/D Rev. 0, 12/2000 DigitalDNA and Mfax are trademarks of Motorola, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate Motorola integrated circuits or integrated
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MC92520
MC92520UM/D
DSLAM configuration AWS
rx bc nbk
TSC 13003
pcr 465
ATML
18751 circuit
BKC International
mpc82 bsdl
nd1 marking code
acm 33221
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CN8237EBGB
Abstract: CX29704 RS8234 RS8235 PCI x1 express PCB dimensions artwork BC 5473
Text: CN8237 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR
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CN8237
OC-12
CN8237
28237-DSH-001-B
CN8237EBGB
CX29704
RS8234
RS8235
PCI x1 express PCB dimensions artwork
BC 5473
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Untitled
Abstract: No abstract text available
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET DESCRIPTION FEATURES CUBIT®-Pro The CUBIT-3 is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CUBIT-3 devices, all
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TXC-05804
TXC-05802B)
TXC-05810)
8/16-bit)
TXC-05804-MB
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Untitled
Abstract: No abstract text available
Text: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2000 REV. 1.0.7 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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XRT7300
XRT7300
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NEC AC08
Abstract: S3043 S3044
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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Untitled
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD98414 2.4 Gbps ATM SONET FRAMER The µPD98414 NEASCOT-P70 is one of ATM LSIs and provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer
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Original
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PD98414
NEASCOT-P70ï
STS-48c/SDH
STM-16c
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TXC-05804-MB
Abstract: sot marking code w17 W17 marking code sot 23
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET CUBIT®-Pro The CUBIT-3™ is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CellBus devices, all
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TXC-05804
TXC-05802B)
CUBIT-622
TXC-05805)
TXC-05810)
8/16-bit)
TXC-05804-MB
sot marking code w17
W17 marking code sot 23
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7 segment display LTS 542
Abstract: lts 543 pin configuration lts 543 data sheet LTS 543 7 segment display 10 pin LTS 543 transmitter circuit in GPR lts 543 series pin diagram lts 542 pin diagram mips16 instruction set lts 543 pin diagram
Text: Preliminary User’s Manual VR4121 64/32-bit Microprocessor µPD30121 Document No. U13569EJ1V0UM00 1st edition Date Published August 1998 N CP(K) Printed in Japan [MEMO] 2 VR3000, VR4000, VR4100, VR4102, VR4111, VR4120, VR4121, VR4300, VR4305, VR4310, VR4400, VR5000,
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VR4121TM
64/32-bit
PD30121
U13569EJ1V0UM00
VR3000,
VR4000,
VR4100,
VR4102,
VR4111,
VR4120,
7 segment display LTS 542
lts 543 pin configuration
lts 543 data sheet
LTS 543
7 segment display 10 pin LTS 543
transmitter circuit in GPR
lts 543 series pin diagram
lts 542 pin diagram
mips16 instruction set
lts 543 pin diagram
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PCI x1 express PCB dimensions artwork
Abstract: 140288 CN8237EBGB CN8236 RS8234 RS8235 RS8254
Text: CN8237 ATM OC12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly ServiceSAR Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR
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CN8237
CN8237
PCI x1 express PCB dimensions artwork
140288
CN8237EBGB
CN8236
RS8234
RS8235
RS8254
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ATM25
Abstract: IDT77V1264L200 ST6200T
Text: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ! ! ! ! ! ! ! ! ! ! ! ! ! Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for
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Original
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IDT77V1264L200
af-phy-040
77V1254L25
144-Pin
PU-144)
77V1264L200
77V1254
25Mb/s
ATM25
IDT77V1264L200
ST6200T
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XRT7300IV
Abstract: HDB3 schematic 0X00 GR-253-CORE GR-499-CORE XRT7300 HDB3 coaxial link LINE25 13E312
Text: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2000 REV. 1.0.6 GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.
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XRT7300
XRT7300
XRT7300IV
HDB3 schematic
0X00
GR-253-CORE
GR-499-CORE
HDB3 coaxial link
LINE25
13E312
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77V1253
Abstract: IDT77V1253
Text: Triple Port PHY Physical Layer for 25.6 and 51.2 Mbps ATM Networks PRELIMINARY IDT77V1253 Integrated Device Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for
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IDT77V1253
af-phy-040
144-pin
77V1253
IDT77V1253
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nrzi clock recovery
Abstract: 77V1254 IDT77V1254 P3TC SF1153
Text: Quad Port PHY Physical Layer for 25.6 and 51.2 Mbps ATM Networks PRELIMINARY IDT77V1254 Integrated Device Technology, Inc. FEATURES DESCRIPTION • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for four 25.6 Mbps ATM channels
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OCR Scan
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PDF
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IDT77V1254
af-phy-040
144-pin
nrzi clock recovery
77V1254
IDT77V1254
P3TC
SF1153
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