HLT28
Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading
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MC10ELT28,
MC100ELT28
HLT28
KLT28
MC10ELT28/D
HLT28
HT28
KLT28
KT28
MC100ELT28
MC10ELT28
MC10ELT28D
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HLT28
Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading
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MC10ELT28,
MC100ELT28
HLT28
KLT28
MC10ELT28/D
HLT28
KLT28
MC100
MC100ELT28
MC10ELT28
transistor k 4110
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led clock circuit diagram
Abstract: ECL IC NAND ic 3842 datasheet DAC ic 0808 pin diagram 3842 smps IC 8 pin ic 3842 MCK12140 application note ADC 10 Ghz 266 XnOR GATE NB3N551
Text: Complete Clock Management Solutions Processor Skew Tuning 1 HCSL TTL-to-PECL Translator Multiplexer LVDS TTL/CMOS LVDS/HCSL Loop Filter VCO 10 ZDB ASIC Memory 1 CMOS/TTL Divider/ Prescaler PE/EQ Processor 9 1 Discrete PLL Blocks Processor 5 1 PECL/CML Phase
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BRD8042-4
BRD8042/D
led clock circuit diagram
ECL IC NAND
ic 3842 datasheet
DAC ic 0808 pin diagram
3842 smps IC
8 pin ic 3842
MCK12140 application note
ADC 10 Ghz
266 XnOR GATE
NB3N551
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vxis
Abstract: No abstract text available
Text: VX3311 Product Specification LVDS 21-bit Channel Link Receiver-85MHz DESCRIPTION ABSOLUTE MAXIMUM RATINGS The VX3311 receiver converts the four LVDS data s treams back into 21 bits of CMOS/TTL data. n n n n Supply voltage CMOS/TTL input voltage CMOS/TTL output voltage
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VX3311
21-bit
Receiver-85MHz
VX3311
vxis
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KLT28
Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Text: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are
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MC10ELT28,
MC100ELT28
MC10ELT/100ELT28
ELT28
r14525
MC10ELT28/D
KLT28
HLT28
HT28
KT28
MC100ELT28
MC10ELT28
transistor k 4110
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PDF
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HLT28
Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading
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Original
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MC10ELT28,
MC100ELT28
HLT28
KLT28
MC10ELT28/D
HLT28
HT28
KLT28
KT28
MC100ELT28
MC10ELT28
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PDF
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Untitled
Abstract: No abstract text available
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading
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MC10ELT28,
MC100ELT28
HLT28
KLT28
MC10ELT28/D
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PDF
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Untitled
Abstract: No abstract text available
Text: SBC84622 AMD LX800 3.5" Embedded SBC with Dual LANs, 4 COM, 4 USB 2.0 and VGA/LVDS/ TTL TTL LCD interface LVDS USB 3/4 Features Low power fanless AMD LX800 processor AMD CS5536AD chipset Dual 10/100Mbps Ethernet supported 4 COM ports and 4 USB 2.0 ports VGA and LVDS/TTL LCD
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SBC84622
LX800
CS5536AD
10/100Mbps
59384500200E
PC/104
250mm
SBC84622VEEA-500
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PDF
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klt28
Abstract: MC10ELT28 HLT28
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are
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MC10ELT28,
MC100ELT28
MC10ELT/100ELT28
ELT28
MC100ELT28
AN1404
AN1405
AN1406
AN1503
klt28
MC10ELT28
HLT28
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KLT28
Abstract: kt28 HLT28 HT28 MC100ELT28 MC10ELT28
Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are
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Original
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MC10ELT28,
MC100ELT28
MC10ELT/100ELT28
ELT28
MC10ELT28/D
KLT28
kt28
HLT28
HT28
MC100ELT28
MC10ELT28
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MC10H605-D
Abstract: MC100H605 MC10H605 MC10H605FN
Text: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source
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MC10H605,
MC100H605
MC10/100H605
MC10H605/D
MC10H605-D
MC100H605
MC10H605
MC10H605FN
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k 3555
Abstract: H607 MC100H607 MC10H607 MC10H607FN
Text: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive
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MC10H607,
MC100H607
MC10H/100H607
10HTM
MC10H607/D
k 3555
H607
MC100H607
MC10H607
MC10H607FN
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MC100H605
Abstract: MC10H605 MC10H605FN
Text: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source
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MC10H605,
MC100H605
MC10/100H605
MC10H605/D
MC100H605
MC10H605
MC10H605FN
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Untitled
Abstract: No abstract text available
Text: 100325 100325 Low Power Hex ECL-to-TTL Translator Literature Number: SNOS129A 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit
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SNOS129A
F100K
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Untitled
Abstract: No abstract text available
Text: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive
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MC10H607,
MC100H607
MC10H/100H607
MC10H607/D
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PDF
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Untitled
Abstract: No abstract text available
Text: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source
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MC10H605,
MC100H605
MC10/100H605
MC10H605/D
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marking code diode wl
Abstract: motorola ECL k 3555 PLCC-28 H607 MC100H607 MC10H607 MC10H607FN
Text: MC10H607, MC100H607 Registered Hex PECL to TTL Translator Description The MC10H/100H607 is a 6−bit, registered PECL to TTL translator. The device features differential PECL inputs for both data and clock. The TTL outputs feature 48 mA sink, 24 mA source drive
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MC10H607,
MC100H607
MC10H/100H607
10HTM
MC10H607/D
marking code diode wl
motorola ECL
k 3555
PLCC-28
H607
MC100H607
MC10H607
MC10H607FN
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H604
Abstract: MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
H604
MC100H604
MC10H604
MC10H604FN
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H604
Abstract: MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
H604
MC100H604
MC10H604
MC10H604FN
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PDF
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Untitled
Abstract: No abstract text available
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
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PDF
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PLCC-28
Abstract: H604 MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
PLCC-28
H604
MC100H604
MC10H604
MC10H604FN
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PDF
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Untitled
Abstract: No abstract text available
Text: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible
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SNOS128A
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Untitled
Abstract: No abstract text available
Text: AX12600 VGA and LCD Display Module Features VGA, TTL LCD and TFT LVDS LCD DualView for different resolutions & contents Direct 3D Acceleration Landscape and Portrait rotation PCI104 SBC Services and Solutions TTL LCD Systems on Modules LVDS Embedded SBCs >EPIC
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AX12600
PCI104
PC/104
SMI712EM+
36-bit
24-bit
DST80
24bpp
24bpp
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PRL-426TTR
Abstract: PRL-426N PRL426PTR PRL-426T PRL-426 sma
Text: PRL-426N DUAL CHANNEL NECL TO LVDS TRANSLATOR PRL-426P DUAL CHANNEL PECL TO LVDS TRANSLATOR PRL-426T DUAL CHANNEL TTL TO LVDS TRANSLATOR APPLICATIONS • Converting Single Ended or Differential NECL/PECL Signals to LVDS Signals • Converting TTL Signals to LVDS
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PRL-426N
PRL-426P
PRL-426T
PRL-426NTR,
PRL-426PTR
PRL-426TTR
PRL-426NTR
PRL-425N
PRL-426
PRL-426TTR
PRL426PTR
PRL-426 sma
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