CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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Untitled
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
CDC318ADLR
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K3638
Abstract: 4Y04
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
K3638
4Y04
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48-PIN
Abstract: CDC318A
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
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k3638
Abstract: No abstract text available
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
k3638
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CDC318
Abstract: CDC318DL CDC318DLR
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
CDC318DL
CDC318DLR
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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CDIP2-T20
Abstract: icc 312 106aa
Text: INCH-POUND MIL-M-38510/338B 10 February 2004 SUPERSEDING MIL-M-38510/338A 22 May 1990 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, ARITHMETIC LOGIC UNITS, MONOLITHIC SILICON Reactivated after 10 February 2004 and may be used for either new or existing design acquisition.
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MIL-M-38510/338B
MIL-M-38510/338A
MIL-M-38510/338B
CDIP2-T20
icc 312
106aa
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Untitled
Abstract: No abstract text available
Text: Ordering number:ENN3029B Monolithic Digital IC LB8902M 3-Channel Clock Driver Overview Package Dimensions • The LB8902M is designed to drive a capacitive load at a high speed. • Suited for horizontal clock drive of CCD image sensor. unit:mm 3097A-MFP16FS
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ENN3029B
LB8902M
LB8902M
097A-MFP16FS
LB8902M]
100pF
MFP16FS
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CDFP2-F14 DIMENSIONS
Abstract: No abstract text available
Text: INCH-POUND MIL-M-38510/315D 27 October 2003 SUPERSEDING MIL-M-38510/315C 17 JANUARY 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW-POWER SCHOTTKY TTL, COUNTERS, MONOLITHIC SILICON Inactive for new design after 18 April 1997. This specification is approved for use by all Departments
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MIL-M-38510/315D
MIL-M-38510/315C
MIL-M-38510/315D
CDFP2-F14 DIMENSIONS
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Untitled
Abstract: No abstract text available
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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CDC318A
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
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Untitled
Abstract: No abstract text available
Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add device type 02. Add packages J and 3 for device type 02. Editorial changes throughout. 93-02-16 Monica L. Poelking B Update to current requirements. Editorial changes throughout. - gap 06-01-05 Raymond Monnin
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MIL-PRF-38535
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daq 6008
Abstract: AM2901C/BQA ABAZ Mostek 6008 2901c AM2901c-BYC PHL22 F0736 UI5 321
Text: D E S C FORM 193 MAY B6 This Material Copyrighted By Its Respective Manufacturer ± 1. SCOPE 1.1 Scope. T h is drawing d e scrio e s d evice renuirem ents fo r c la s s B m ic r o c ir c u it s in accordance with
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oTlilL-STO-883,
MIL-STD-883
MIL-M-38510
2901C
TS29010ICB/C
TS2901CMJB/C
701ZX
AM2901C/BYC
daq 6008
AM2901C/BQA
ABAZ
Mostek 6008
AM2901c-BYC
PHL22
F0736
UI5 321
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA Military 54LS181 4-Bit Arithmetic Logic Unit MPO mini ELECTRICALLY TESTED PER: MIL-M-35810/30801 T h e 54LS181 is a 4 -b it A rith m etic L ogic U nit (ALU ) w hich can perform all th e possib le 16 logic o pe ra tio ns on tw o va ria b le s and a v a rie ty of
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54LS181
MIL-M-35810/30801
54LS181
1PLH12
PLH12
tPHL13
PHL13
1PLH13
PLH13
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marking code ADg
Abstract: ic 76 adg l7 723 M/A relay lzl T7895 aos Lot Code Identification n7t marking iwatt marking
Text: MIL-M-38510/520B 20 JUNE 1983 W L R S E DING-MIL-M-38510/520A 9 D e c e m b e r 1982 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, MONOLITHIC N-CHANNEL, SILICON GATE 16-BIT M I C R O PR OC ES SO R T h i s s p e c i f i c a t i o n is a p p r o v e d f o r u s e b y all D e p a r t
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MIL-M-38510/520B
MIL-M-38510/520A
16-BIT
MIL-M-38510.
Z8001
Z8002
Z8001A
Z8002A
marking code ADg
ic 76 adg
l7 723 M/A
relay lzl
T7895
aos Lot Code Identification
n7t marking
iwatt marking
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A M ilita ry 54ALS161 Synchronous 4-Bit Binary Counter (With Asynchronous Clear) ELECTRICALLY TESTED PER: MPG54ALS161 AVAILABLE AS: The ALS161 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable MSI building
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54ALS161
MPG54ALS161
ALS161
tPHL12
tpHL13
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hl43
Abstract: TIL413 IZ6 data sheet PJ 3139 B38G 2901c marking AYB
Text: I QUALI FI CAI 1ÜTTI I REQUIREMENTS I REMOVED M I I MILITARY MICROCIRCUITS, DIGITAL, T h i s s p e c i f i c a t i o n is ments and Agencies should be FOUR-31T noted that previous MICROPROCESSOR Scope. This reflected approved of the f o r u s e by Department
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MIL-M-38510/440B
M1L-M-38510,
HIL-H-38510/440C
hl43
TIL413
IZ6 data sheet
PJ 3139
B38G
2901c
marking AYB
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smlx
Abstract: 2901c ABAZ daq 6008 phl40 LH27
Text: D E S C FORM 193 MAY B6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ± 1. SCOPE 1.1 Scope. This drawing descrioes device renuirements fo r c la s s B m icro circu its in accordance with
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oTlilL-STO-883,
MIL-STD-883
MIL-M-38510
2901C
designate00
TS29010ICB/C
TS2901CMJB/C
701ZX
AM2901C/Ã
smlx
ABAZ
daq 6008
phl40
LH27
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Untitled
Abstract: No abstract text available
Text: CDC318A l-LINE TO 18-LINE CLOCK DRIVER WITH |2C CONTROL INTERFACE SC AS 614 - SE P TE M B E R 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 500 ps
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CDC318A
18-LINE
1-to-18
100-MHz
MIL-STD-883,
48-Pin
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6358NS
Abstract: No abstract text available
Text: M Military 54LS192 M O TO R O LA Presettable BCD/Decade UP/Down Counter ELECTRICALLY TESTED PER: MIL-M-38510/31507 M U HM The 54LS192 is an UP/DOWN BCD Decade (8421) Counter and the 54LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the
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54LS192
MIL-M-38510/31507
54LS192
54LS193
MODULO-16
tPHL13
tPHL14
PHL14
PLH14
tPLH14
6358NS
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8300102qx
Abstract: phl24
Text: iD I S T R I B y T I O N S T A T E M E N T iA i_ A p p ro v e d fo r p u b lic re le a se ; d is tr ib u tio n is u n lim ite d . DESC FORM 193 MAY 86 1. SCOPE 1.1 Scope. T h is draw ing d e s c rib e s d e v ic e re q u ire m e n ts f o r c la s s B m ic r o c ir c u i t s in acco rdan ce
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MIL-STD-883,
MIL-STD-883
MIL-M-38510
Z8536/Z0853604
Z8536number
8300101QX
IZ0853604CMB
8300101YX
Z0853604LMB
8300102QX
phl24
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA Military 54LS181 4-Bit Arithmetic Logic Unit ELECTRICALLY TESTED PER: MIL-M-35810/30801 H P O /////// T h e 54LS181 is a 4 -b it A rith m e tic Logic U nit (ALU ) w hich can perform all th e p ossib le 16 logic o pe ra tion s on tw o va ria b le s and a va rie ty of
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MIL-M-35810/30801
54LS181
54LS181
tPHL11
tPHL11
PLH11
tPLH11
tPHL12
tPLH12
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