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    Amphenol ProLabs TN-10GSFP-SR-C

    Transition Networks TN-10GSFP-SR
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    DigiKey TN-10GSFP-SR-C 39,776 1
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    Murata Manufacturing Co Ltd LQP02TN10NH02D

    FIXED IND 10NH 140MA 2.5 OHM SMD
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    ATGBICS TN-10GSFP-SR-C

    Compatible SFP+ 10G
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    Mitsubishi Materials Corporation TN10-3K473JT

    NTC CHIP THERMISTOR 47KOHM 3500K
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    Eaton Bussmann STN102050UL80

    TVS DIODE 5VWM 12VC DFN1006-2L
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    TN10 Datasheets (84)

    Part ECAD Model Manufacturer Description Curated Type PDF
    TN100 STMicroelectronics High performance CSS transceiver enabling location awareness Original PDF
    TN100A Topstek Topstek Current Transducers Original PDF
    TN100Q STMicroelectronics High performance CSS transceiver enabling location awareness Original PDF
    TN100Q STMicroelectronics High performance CSS transceiver enabling location awareness Original PDF
    TN100QT STMicroelectronics High performance CSS transceiver enabling location awareness Original PDF
    TN100QT STMicroelectronics High performance CSS transceiver enabling location awareness Original PDF
    TN-101 Clare MICROWAVE NOISE TUBE Original PDF
    TN101 High Energy Devices TD / TN Series - Microwave Noise Tubes & Noise Sources Original PDF
    TN-102 Clare MICROWAVE NOISE TUBE Original PDF
    TN102 High Energy Devices TD / TN Series - Microwave Noise Tubes & Noise Sources Original PDF
    TN10-20-1/420-1 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/4" Original PDF
    TN10-20-1/420-2 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/4" Original PDF
    TN10-20-1/420-3 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/4" Original PDF
    TN10-24-1/420-1 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/2" Original PDF
    TN10-24-1/420-2 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/2" Original PDF
    TN10-24-1/420-3 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-1/2" Original PDF
    TN10-28-1/420-1 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-3/4" Original PDF
    TN10-28-1/420-2 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-3/4" Original PDF
    TN10-28-1/420-3 Essentra Components Catalog Board Spacers, Standoffs, Hardware, Fasteners, Accessories, RND STANDOFF 1/4-20 NYLON 1-3/4" Original PDF
    TN10-2D300JB Mitsubishi Thermistor NTC 30OHM 5% Original PDF

    TN10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    h420

    Abstract: DS1004 MPC860 0x00034 0X00005
    Text: LatticeSC MPI/System Bus April 2010 Technical Note TN1085 Introduction The embedded system bus on the LatticeSC ties all of the programmable elements together in a bus framework. There are two types of interfaces on the system bus, master and slave. A master interface has the ability to perform


    Original     		PDF TN1085 0x36085, 0x36085) 0x00010) 0x00012. h420 DS1004 MPC860 0x00034 0X00005

    CITS25

    Abstract: wl gore DXSN2112 Mictor amp TN1068 BLM41P ORT82G5 TN1066 10-22uf MURATA BLM41P
    Text: 高速印刷电路板的设计考虑 2006 年 12 月 技术说明 TN1033 简介 背板是一种典型的用于系统内汇集所有电子模块的物理互连的方式。复杂的系统依靠背板上的连线走线和连接器 来处理大量的高速数据。多个背板模块之间的通信受到诸如连接器、走线长度、过孔和终端等部件的阻抗、电容以


    Original     		PDF TN1033 tn1033 4350GETEK LatticeECP2/MORT82G5 850Mbps Si6000b ORT82G5 TN1027 ORT42G5 CITS25 wl gore DXSN2112 Mictor amp TN1068 BLM41P ORT82G5 TN1066 10-22uf MURATA BLM41P

    PFU1

    Abstract: TN1010 TN1012 signal path designer
    Text: Constraining ORCA Designs March 2002 Technical Note TN1012 Introduction Design constraints are one of the most important aspects of an FPGA design. Along with a good functional design, design constraints are directly tied to the success of device validation on the system board. FPGA designs also


    Original     		PDF TN1012 1-800-LATTICE PFU1 TN1010 TN1012 signal path designer

    ATT ORCA fpga architecture

    Abstract: DB9 jtag cable ATT ORCA fpga 9-pin female connector on board 7Pin din Connector on which pin to connect vcc in db9 connector standard 6-pin JTAG header ATT ORCAs female PCB connector 2x5 7Pin Connector
    Text: ORCA Device Programming Download Cable July 2002 Technical Note TN1009 Introduction The ORCA device family offers many programming options for device configuration. Users can easily incorporate the ORCA Download Cable into their system designs, integrating several modes into one easy-to-use interface for


    Original     		PDF TN1009 ATT ORCA fpga architecture DB9 jtag cable ATT ORCA fpga 9-pin female connector on board 7Pin din Connector on which pin to connect vcc in db9 connector standard 6-pin JTAG header ATT ORCAs female PCB connector 2x5 7Pin Connector

    LVCMOS25

    Abstract: LVCMOS33 clock select adder with sharing TN1001 tgo-e
    Text: ispMACH 5000VG Timing Model Design and Usage Guidelines November 2001 Technical Note TN1001 Introduction Understanding how the placement of the design influences timing is essential when designing into the ispMACH 5000VG family. A signal in the device can take several paths, where each different path affects timing in some manner. This application note explains the ispMACH 5000VG timing model and offers a few techniques to enhance


    Original     		PDF 5000VG TN1001 68-input, 32-macrocell 5000VG. LVCMOS25 LVCMOS33 clock select adder with sharing TN1001 tgo-e

    INTRODUCTION OF AUTOMATIC ROOM power CONTROL

    Abstract: TN1041
    Text: ispXP Technology Power-up and Hot Socketing December 2002 Technical Note TN1041 Introduction The ispXP eXpanded in-system Programmable device families from Lattice offer the non-volatility of E2 cells together with the infinite reconfigurability of SRAM. This is achieved by the one-to-one relationship between SRAM


    Original     		PDF TN1041 1-800-LATTICE INTRODUCTION OF AUTOMATIC ROOM power CONTROL TN1041

    vhdl code for loop filter of digital PLL

    Abstract: vhdl code for lvds driver vhdl code for clock and data recovery 8B10B 8B10B in serial communication CDRPLL TN1000 vhdl code for phase shift vhdl code for lvds receiver
    Text: sysHSI Block Usage Guidelines October 2003 Technical Note TN1020 Introduction As demand for bandwidth increases in this information-based society, communications systems with advanced technologies are emerging to meet such demand. Embedding clocks into serial data streams is a popular technique in high-speed data communications systems applications. The embedded clock is recovered at the receiver


    Original     		PDF TN1020 10B12B 8B10B 1-800-LATTICE vhdl code for loop filter of digital PLL vhdl code for lvds driver vhdl code for clock and data recovery 8B10B in serial communication CDRPLL TN1000 vhdl code for phase shift vhdl code for lvds receiver

    CITS25

    Abstract: FR4 epoxy dielectric constant 4.2 Gore eye opener FR4 microstrip stub DXSN2112 mictor connector layout guideline ORLI10G ORSO42G5 ORSO82G5 ORT42G5
    Text: High-Speed PCB Design Considerations February 2004 Technical Note TN1033 Introduction The backplane is the physical interconnection where typically all electrical modules of a system converge. Complex systems rely on the wires, traces, and connectors of the backplane to handle large amounts of data at high speeds.


    Original     		PDF TN1033 ORT8850H/L ORLI10G ORT82G5, Si6000b ORT82G5 TN1027 ORT42G5 ORSO82G5 CITS25 FR4 epoxy dielectric constant 4.2 Gore eye opener FR4 microstrip stub DXSN2112 mictor connector layout guideline ORSO42G5

    crc 16 verilog

    Abstract: cyclic redundancy check verilog source
    Text: ispXP Configuration Usage Guidelines August 2002 Technical Note TN1026 1. Introduction Traditional programmable logic devices incorporate either E2CMOS memory or SRAM for storage of the configuration data used to define the device functionality. Each technology has its advantages and disadvantages.


    Original     		PDF TN1026 1-800-LATTICE crc 16 verilog cyclic redundancy check verilog source

    vhdl code for register

    Abstract: ORT82G5
    Text: Accessing ORT82G5 Configuration Registers via the User Master Interface April 2003 Technical Note TN1038 Introduction The Lattice ORT82G5 Backplane Transceiver FPSC features many user-defined options and status indicators. These options and indicators are accessed through memory-mapped registers within the device. These 8-bit memory locations define and monitor various operations and states within the FPSC core. The memory structure is


    Original     		PDF ORT82G5 TN1038 300xx 301xx 308xx 309xx 30A0x vhdl code for register

    AR-17

    Abstract: AW12 Q110 Q117 RAM1024 scuba ar17
    Text: ORCA Series 4 Quad-Port Embedded Block RAM August 2002 Technical Note TN1016 Introduction The ORCA Series 4 FPGA platform provides embedded block RAM EBR macrocells to compliment it’s distributed PFU RAM. By using ORCA Series 4 EBR, designers can realize the benefits of system-on-a- chip (SoC) and


    Original     		PDF TN1016 512x18 AR-17 AW12 Q110 Q117 RAM1024 scuba ar17

    multiplier accumulator MAC code verilog

    Abstract: multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog
    Text: LatticeECP-DSP sysDSP Usage Guide October 2005 Technical Note TN1057 Introduction This technical note discusses how to access the features of the LatticeECP -DSP sysDSP™ Digital Signal Processing Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an example of the


    Original     		PDF TN1057 LFECP20E-5 LFEC20E-5 18x18 multiplier accumulator MAC code verilog multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog

    AC22

    Abstract: AC25 Signal Path Designer
    Text: ORCA Series 4 FPGA PLL Elements September 2004 Technical Note TN1014 Introduction The ORCA Series 4 FPGA platform has been designed for the delivery of networking IP, with improved performance and decreased time-to-market. To facilitate the feature-rich, high-speed architecture of the Series 4, and to support the fast-paced networking markets, fixed and programmable phase-locked loop PLL components have been embedded in each Series 4 array.


    Original     		PDF TN1014 AC22 AC25 Signal Path Designer

    310CB

    Abstract: transistor 30945 30945 30A27 k3264 TN1073 30A07 30A45
    Text: ORSPI4 Provisioning September 2004 Technical Note TN1073 Introduction The ORSPI4 is a next generation FPSC targeted at high speed data transmission, built on the Series 4 reconfigurable embedded System-on-Chip SoC architecture. The ORSPI4 device has been designed to support a broad


    Original     		PDF TN1073 310CB transistor 30945 30945 30A27 k3264 TN1073 30A07 30A45

    vhdl code for 4 bit ripple COUNTER

    Abstract: verilog advantages disadvantages verilog codes for full adder vhdl code for 16 BIT BINARY DIVIDER verilog code power gating verilog code divide verilog hdl code for LINEAR BLOCK CODE 8 bit carry select adder verilog codes 8 bit sequential multiplier VERILOG 4 bit binary multiplier Vhdl code
    Text: HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs October 2005 Technical Note TN1008 Introduction Coding style plays an important role in utilizing FPGA resources. Although many popular synthesis tools have significantly improved optimization algorithms for FPGAs, it still is the responsibility of the user to generate meaningful


    Original     		PDF TN1008 1-800-LATTICE vhdl code for 4 bit ripple COUNTER verilog advantages disadvantages verilog codes for full adder vhdl code for 16 BIT BINARY DIVIDER verilog code power gating verilog code divide verilog hdl code for LINEAR BLOCK CODE 8 bit carry select adder verilog codes 8 bit sequential multiplier VERILOG 4 bit binary multiplier Vhdl code

    TN100

    Abstract: TN100-MOD ADC12 PA13 PA15 PC13 STM32 15050RF
    Text: TN100-MOD TN100 RF module Target Specification Features • TN100 transceiver ■ STM32 microcontroller ■ Matching circuits balun ■ Integrated 2.4 GHz chip antenna ■ ISM band pass filter ■ 32.768 kHz, 16 MHz, and 32 MHz quartz crystals c u d Peripherals


    Original     		PDF TN100-MOD TN100 STM32 TN100-MOD ADC12 PA13 PA15 PC13 15050RF

    Untitled

    Abstract: No abstract text available
    Text: TN100 High performance CSS transceiver enabling location awareness Preliminary Data Features • Single-chip solution for ISM 2.45 GHz RF transceiver ■ Built-in ranging capability for link distance estimation ■ Modulation technique: chirp spread spectrum


    Original     		PDF TN100

    802.15.4a

    Abstract: Nanotron Technologies 60870-5-1 CRC nanotron TN1007 Chirp Spread Spectrum VFQFPN2-48 TN100 JESD97 Q121
    Text: TN100 High performance CSS transceiver enabling location awareness Preliminary Data Features • Single-chip solution for ISM 2.45 GHz RF transceiver ■ Built-in ranging capability for link distance estimation ■ Modulation technique: chirp spread spectrum


    Original     		PDF TN100 802.15.4a Nanotron Technologies 60870-5-1 CRC nanotron TN1007 Chirp Spread Spectrum VFQFPN2-48 TN100 JESD97 Q121

    turbo C programming

    Abstract: TN1019 ISPVM AN6062 "EZ-USB"
    Text: Multiple Board Programming Using ispVM System-DlxConnect August 2004 Technical Note TN1075 Introduction This technical note describes the methodologies available for programming Lattice devices on multiple printed circuit boards gang programming . The first section of this document describes how to use the ispVM-DLxConnect


    Original     		PDF TN1075 TN1019, AN6062, 1-800-LATTICE turbo C programming TN1019 ISPVM AN6062 "EZ-USB"

    pfu3

    Abstract: vhdl code for 4 bit ripple COUNTER data flow vhdl code for ripple counter TN1010 vhdl code complex multiplier system design using pll vhdl code verilog code for 4 bit ripple COUNTER
    Text: Lattice Semiconductor Design Floorplanning July 2004 Technical Note TN1010 Introduction Lattice Semiconductor’s ispLEVER software, together with Lattice Semiconductor’s catalog of programmable devices, provides options to help meet design timing and logic utilization requirements. Additionally, for those


    Original     		PDF TN1010 TN1018, 1-800-LATTICE pfu3 vhdl code for 4 bit ripple COUNTER data flow vhdl code for ripple counter TN1010 vhdl code complex multiplier system design using pll vhdl code verilog code for 4 bit ripple COUNTER

    sdram pcb layout guide

    Abstract: vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4
    Text: LatticeECP/EC and LatticeXP DDR Usage Guide February 2007 Technical Note TN1050 Introduction LatticeECP , LatticeEC™ and LatticeXP™ devices support various Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one


    Original     		PDF TN1050 200MHz LatticeEC20 sdram pcb layout guide vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4

    Thermonics T-2500

    Abstract: thermostream EYE DIAGRAM thermonics HPE3630A ORSO42G5 ORSO82G5 ORT42G5 ORT82G5 10GEC
    Text: ORTx2G5, ORSOx2G5 and ORSPI4 High-Speed Backplane Measurements July 2004 Technical Note TN1027 Introduction The Lattice ORT82G5 and ORSO82G5 FPSC devices contain two Quad-SERDES blocks. The Lattice ORT42G5, ORSO42G5 and ORSPI4 FPSC devices contain one Quad-SERDES block. Each SERDES SERializer/DESerializer provides a serial high-speed backplane transceiver interface, operational at data rates up to 3.7 Gbit/s for the


    Original     		PDF TN1027 ORT82G5 ORSO82G5 ORT42G5, ORSO42G5 10GEC TN1032 TN1033 Thermonics T-2500 thermostream EYE DIAGRAM thermonics HPE3630A ORT42G5 10GEC

    hdc 3076

    Abstract: No abstract text available
    Text: ORCA Series 4 FPGA Configuration April 2002 Technical Note TN1013 Introduction Configuration is the process of loading a design via a bitstream file into the FPGA internal configuration memory. Readback is the process of reading the configuration data in a programmed FPGA back out, into a file.


    Original     		PDF TN1013 hdc 3076

    N105PH12

    Abstract: No abstract text available
    Text: Technical WESTCODE ® SEMICONDUCTORS Publication TN105P/R Issue 2 July 1985 Convertor Grade Stud-Base Thyristor Type N105P/N105R 110 amperes average: up to 1500 volts V rrm Ratings M a x im u m values a t 125°C Tj unless stated otherw ise SYM B O L R A TIN G


    OCR Scan     		PDF TN105P/R N105P/N105R N105PH12