MX98741
Abstract: No abstract text available
Text: INDEX MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports
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Original
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MX98741
208-pin,
PM0342
MX98741
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PDF
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T05A
Abstract: MX98741 MX98742 MX98745
Text: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display
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Original
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MX98745
MX98745
MX98745,
PM0427
T05A
MX98741
MX98742
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PDF
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MC68836
Abstract: MX98741 MX98742 MX98745 AM78965
Text: PRELIMINARY MX98745 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • IEEE 802.3u D5 repeater and management compatible • Support 7 TX/FX ports and 1 universal port TX or MII port selectable • Support 8-scale utilization and collision rate LED display
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Original
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MX98745
MX98745
MX98745,
PM0427
MC68836
MX98741
MX98742
AM78965
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PDF
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nrzi to nrz converter circuit diagram
Abstract: nrzi TDAT40 kd212 XFORMER MX98702 MX98704 MX98704QC MX98713 MX98741
Text: INDEX PRELIMINARY MX98704 100BASE-TX PHYSICAL DATA TRANSCEIVER 1.0 FEATURES • • • • • • • • • • • Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data
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Original
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MX98704
100BASE-TX
125-Mhz
25-Mhz
100Base-Tx
nrzi to nrz converter circuit diagram
nrzi
TDAT40
kd212
XFORMER
MX98702
MX98704
MX98704QC
MX98713
MX98741
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PDF
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6K8k
Abstract: t41 datasheet 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13 2-port bridge fiber UTP
Text: INDEX PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port
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Original
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MX98742
10BASE
512-bit
6K8k
t41 datasheet
MX98741
MX98742
SA10
SA11
SA12
SA13
2-port bridge fiber UTP
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PDF
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mlt 22 612
Abstract: nrzi clock recovery mlt resistor MX98705 mlt 44 pin
Text: PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package
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Original
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MX98705
MX98705
100Base-TX
52--Pin
PM0471
mlt 22 612
nrzi clock recovery
mlt resistor
mlt 44 pin
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PDF
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6K8k
Abstract: AM79866 broadcom 1024 10BASE MX98741 MX98742 SA10 SA11 SA12 SA13
Text: PRELIMINARY MX98742 FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES * * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port
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Original
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MX98742
10BASE
512-bit
PM0403
6K8k
AM79866
broadcom 1024
MX98741
MX98742
SA10
SA11
SA12
SA13
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PDF
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jami
Abstract: XRC circuit diagram 128-PIN MX98741 MX98745 MX98746
Text: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM
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Original
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MX98746
MX98746
128-PIN
MX98746.
PM0478
jami
XRC circuit diagram
MX98741
MX98745
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PDF
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128-PIN
Abstract: MX98741 MX98745 MX98746
Text: INDEX PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • Separate jabber and partition state machines for each port • On-chip elasticity buffer for PHY signal re-timing to the MX98746 clock source • Contents of internal register loaded from EEPROM
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Original
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MX98746
MX98746
128-PIN
MX98746.
PM0478
MX98741
MX98745
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PDF
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nrzi to nrz converter circuit diagram
Abstract: nrzi to nrz circuit diagram MX98705 Mlt-3
Text: INDEX PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package
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Original
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MX98705
MX98705
100Base-TX
52--Pin
PM0471
nrzi to nrz converter circuit diagram
nrzi to nrz circuit diagram
Mlt-3
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PDF
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crsa 58
Abstract: MX98741
Text: MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface MII • Expandable to increase number of repeater ports
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Original
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MX98741
208-pin,
PM0342
crsa 58
MX98741
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PDF
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nrzi to nrz circuit diagram
Abstract: nrzi to nrz converter circuit diagram MXIC MX mxic
Text: 1 OOBASETX PHYSICAL DATA TRANSCEIVER 1.0 FEATURES • • • • • • • • • • • Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data
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OCR Scan
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125-Mhz
25-Mhz
100Base-Tx
52-PIN
MX98704
nrzi to nrz circuit diagram
nrzi to nrz converter circuit diagram
MXIC MX
mxic
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PDF
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Untitled
Abstract: No abstract text available
Text: FVeliminaiy n Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • Line state detection ■ ■ Hardware Physical Connection Management (PCM) support
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OCR Scan
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Am79C864
5535-043A
14977-050B
14977-051B
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PDF
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T-75-49
Abstract: AM79865 AMD Supernet 2 AM79866JC MAE 411
Text: ADV MICRO T E L E C O M MAE D □ 257527 0 0 3 0 ^ 2 □ • AMD3 Preliminary a Advanced Micro Devices Am79865/Am79866 Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS ■ ■ ■ ■ Parallel Input to the PDT Is a 5-bit encoded
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OCR Scan
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Am79865/Am79866
20-pin
02S7527
003100b
T-75-49
5451-012A
5451-013A
T-75-49
AM79865
AMD Supernet 2
AM79866JC
MAE 411
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES Five Bit TTL Nibble at 25 MHz Input/Output 25 MHz received recovery clock Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB Single +5V Supply 52 PQFP package • Complies with IEEE 802.3 Standards
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OCR Scan
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MX98705
MX98705
10OBase-TX
RJ-45
PM0471
Pin39
Pin34
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PDF
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Untitled
Abstract: No abstract text available
Text: H Preliminary Advanced Micro Devices Am79865/Am79866 Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Parallel Input to the PDT Is a 5-bit encoded NRZ symbol clocked by LSCLK Parallel output from the PDR Is a 5-bit
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OCR Scan
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Am79865/Am79866
20-pin
Laye010A
IN916
IN3064,
5451-012A
5451-013A
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PDF
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Untitled
Abstract: No abstract text available
Text: a P R E L IM IN A R Y Advanced Micro Devices Am79865/Am79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Parallel Input to the PDT is a 5-blt encoded NRZ symbol clocked by LSCLK 125 MBaud 100 Mbps serial link data rate
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OCR Scan
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Am79865/Am79866A
20-pin
IN916
IN3064,
FDD11994
15451C-12
02S7527
0033ST2
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PDF
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Untitled
Abstract: No abstract text available
Text: Preliminary Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and
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OCR Scan
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Am79C864
5535-043A
14977-050B
14977-051B
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY MX98746 100 BASE-TX/FX 5-PORT CLASSII REPEATER CONTROLLER 1.0 FEATURES • S eparate ja b b e r and partition state m achines fo re a c h port • O n-chip e la sticity buffer fo r PHY signal re-tim ing to the M X 98746 clo ck source •C o n te n ts of internal register loaded from EEPRO M
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OCR Scan
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MX98746
MX98746,
PM0478
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PDF
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Untitled
Abstract: No abstract text available
Text: MXIC _M X 9 8 7 4 2 FEBC 1 OO BASE FAST ETHERNET BRIDGE CONTROLLER 1.0 FEATURES 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, Mil interfaces, and 10BASE serial port
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OCR Scan
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10BASE
512-bit
MX98742
25MHz
160-Pin
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PDF
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