CR21
Abstract: GR-499-CORE TBR24 XRT71D00 XRT7300 XRT7302 XRT73L03 role of microprocessor
Text: XRT71D00 PRELIMINARY DS3/E3 JITTER ATTENUATOR IC OCTOBER 1999 REV. 1.0.6 FEATURES • Meets output jitter generation requirement as spec- ified by ETSI TBR24 • A single-chip that does the following: • Accepts “jittery” clock and data from an LIU IC
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XRT71D00
TBR24
TBR24
34Mbit/s
XRT71D00ID
XRT71D00IQ32
CR21
GR-499-CORE
XRT71D00
XRT7300
XRT7302
XRT73L03
role of microprocessor
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HDB3 matlab
Abstract: block diagram prbs generator in matlab matlab pn sequence generator HP54502A
Text: DART Device Advanced E3/DS3 Receiver/Transmitter TXC-02030 FEATURES DESCRIPTION • Single LIU for E3 and DS3 The Dual-market Advanced E3/DS3 Receiver/Transmitter DART device performs the receive and transmit line interface functions required for transmission of E3
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TXC-02030
TXC-02030-MB
HDB3 matlab
block diagram prbs generator in matlab
matlab pn sequence generator
HP54502A
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TIC126 equivalent
Abstract: BCR40 93C46 AM79C978A PC99 of finite state machine AM79C901A
Text: Am79C978A PCnet - Home Single-Chip 1/10 Mbps PCI Home Networking Controller DISTINCTIVE CHARACTERISTICS n Fully integrated 1 Mbps HomePNA Physical Layer PHY as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Optimized for home networking applications
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Am79C978A
Index-10
TIC126 equivalent
BCR40
93C46
PC99
of finite state machine
AM79C901A
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CX28331
Abstract: CX28332 CX28333 TBR24 48-ETQFP AMI 52 732 V
Text: Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit Data Sheet CX28331/CX28332/CX28333 –3x 28333-DSH-002-B Feb 2003 Revision History Revision Level Date Description A — 6/2001 Initial Release [Document number 28333-DSH-002-A] B — 2/2003 Removed CX2833i-1x information (see separate document)
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CX28331/CX28332/CX28333
28333-DSH-002-B
28333-DSH-002-A]
CX2833i-1x
00371A
CX28331
CX28332
CX28333
TBR24
48-ETQFP
AMI 52 732 V
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AM79C901A
Abstract: 79C901 TIC106
Text: PRELIMINARY Am79C901A HomePHY Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS n Fully integrated 1 Mbps HomePNA Physical Layer PHY as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Optimized for home networking applications
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Am79C901A
RLL25
22304C
79C901
TIC106
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yx 801
Abstract: yx 801 led yx 801 led driver BCR40 IC yx 801 led driver yx 801 led pl 93C46 PC97 PQL144 PQR160
Text: Am79C978 PCnet - Home Single-Chip 1/10 Mbps PCI Home Networking Controller DISTINCTIVE CHARACTERISTICS n Fully integrated 1 Mbps HomePNA Physical Layer PHY as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Supports both PCI 5.0-V and 3.3-V signaling
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Am79C978
yx 801
yx 801 led
yx 801 led driver
BCR40
IC yx 801 led driver
yx 801 led pl
93C46
PC97
PQL144
PQR160
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ANSI T1.102
Abstract: 728A filter EASY3452 GR-499-CORE pulse shaper QUADLIU - PEB 22504
Text: P R O D U C T B R I E F DS3/STS-1/E3 Line Interface Unit The TE3-LIU former PUCCINI; PEB 3452 is a DS3 / STS-1 / E3 Line Interface Unit. It interfaces DS3 / STS-1 / E3 framer device to the analog transmission line. It fulfills the relevant standards for DS3 (44.736 Mbit/s), STS-1 (51.840 Mbit/s) and
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B119-H7614-G1-X-7600
ANSI T1.102
728A filter
EASY3452
GR-499-CORE
pulse shaper
QUADLIU - PEB 22504
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75l00d
Abstract: No abstract text available
Text: áç XRT75L00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 REV. 1.0.1 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION The XRT75L00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer
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XRT75L00D
XRT75L00D
75l00d
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Untitled
Abstract: No abstract text available
Text: XRT75L04 xr FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR JANUARY 2006 GENERAL DESCRIPTION The XRT75L04 is a four-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/DS3/ STS-1 applications. It incorporates four independent
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XRT75L04
XRT75L04
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Untitled
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
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Untitled
Abstract: No abstract text available
Text: áç XRT71D04 PRELIMINARY 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D04 is a four channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore
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XRT71D04
XRT71D04
TBR-24,
GR-499
GR-253
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Untitled
Abstract: No abstract text available
Text: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,
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XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
755oration
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34.368Mhz oscillator
Abstract: chn 543
Text: XRT75L03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR JULY 2003 GENERAL DESCRIPTION The XRT75L03 is a three-channel fully integrated Line Interface Unit LIU with Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates 3
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XRT75L03
XRT75L03
34.368Mhz oscillator
chn 543
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chn 923
Abstract: No abstract text available
Text: xr XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR MARCH 2005 REV. 1.0.7 GENERAL DESCRIPTION TRANSMITTER: The XRT75R03 is a three-channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)
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XRT75R03
XRT75R03
chn 923
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M28335-13P
Abstract: M28335 ferrite RM6 CX28365 M28335EBGC TBR24 DIMENSIONAL STANDARD AH31 AK20 ferrite e16 ferrite transformer ch9i
Text: Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. M28335 Twelve Port T3/E3/STS-1 Line Interface Unit The M28335 is a 12-channel, T3/E3/STS-1 Line Interface Unit LIU . It is configured via a
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M28335
M28335
12-channel,
GR253,
TA-NWT-000253)
TR-TSY-000191,
TBR24
TBR25
TR54014,
M28335-13P
ferrite RM6
CX28365
M28335EBGC
DIMENSIONAL STANDARD AH31
AK20 ferrite e16 ferrite transformer
ch9i
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DMO11
Abstract: DMO10 0X00 GR-253 GR-499-CORE XRT73R12 XRT73R12IB em7 120 cc11r
Text: XRT73R12 PRELIMINARY TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. P1.0.3 GENERAL DESCRIPTION The XRT73R12 provides a Parallel Microprocessor Interface for programming and control. The XRT73R12 is a twelve channel fully integrated Line Interface Unit LIU featuring EXAR’s R3
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XRT73R12
XRT73R12
DMO11
DMO10
0X00
GR-253
GR-499-CORE
XRT73R12IB
em7 120
cc11r
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ATM timing diagram
Abstract: addressing mode motorola 68000 hdlc LAN switch with HDLC GR-253 GR-499-CORE PC403 XRT79L74 XRT79L74IB
Text: PRELIMINARY XRT79L74 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC MARCH 2004 HARDWARE MANUAL The XRT79L74 is a four channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct
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XRT79L74
XRT79L74
ATM timing diagram
addressing mode motorola 68000
hdlc
LAN switch with HDLC
GR-253
GR-499-CORE
PC403
XRT79L74IB
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chn 834
Abstract: CHN 833 CR69 0X00 GR-253 GR-499-CORE XRT75R12D XRT75R12DIB CHN 703 GR-253 J0 byte length 14
Text: XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DECEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT75R12D is a twelve channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)
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XRT75R12D
XRT75R12D
chn 834
CHN 833
CR69
0X00
GR-253
GR-499-CORE
XRT75R12DIB
CHN 703
GR-253 J0 byte length 14
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CHN 703
Abstract: diode ja8 75R12 AS11D eh3 encoder DMO10 DMO11 JA8R GR-253 GR-499-CORE
Text: XRT75R12 PRELIMINARY TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR OCTOBER 2003 REV. P1.0.2 GENERAL DESCRIPTION attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. The XRT75R12 is a twelve channel fully integrated
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XRT75R12
TBR-24
GR-499
XRT75R12
CHN 703
diode ja8
75R12
AS11D
eh3 encoder
DMO10
DMO11
JA8R
GR-253
GR-499-CORE
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hdlc
Abstract: IBM POS GR-253 GR-499-CORE PC403 XRT79L72 XRT79L72IB
Text: xr PRELIMINARY XRT79L72 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC FEBRUARY 2005 HARDWARE MANUAL The XRT79L72 is a two channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct
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XRT79L72
XRT79L72
hdlc
IBM POS
GR-253
GR-499-CORE
PC403
XRT79L72IB
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HDB3 CODING DECODING FPGA
Abstract: chn 834 chn 832 R13C7 CHN 833 GR-253 GR-253-CORE GR-499-CORE XRT75R06D FPGA AMI coding decoding
Text: áç XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/
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XRT75R06D
XRT75R06D
HDB3 CODING DECODING FPGA
chn 834
chn 832
R13C7
CHN 833
GR-253
GR-253-CORE
GR-499-CORE
FPGA AMI coding decoding
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TXN612
Abstract: MT 8222 t1e8 AMI 8531
Text: + DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 457 meters 1500 feet of 75Ω Coaxial Cable
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DS32506/DS32508/DS32512
6-/8-/12-Port
DS32506
DS32508
DS32512
DS32512,
DS32508,
DS32506
TXN612
MT 8222
t1e8
AMI 8531
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tokin 0.47f 5.5v
Abstract: NEC tokin 0,22F tokin 108 tokin 473
Text: FC Series Features Dimensions • Enables surface mounting. D ± 0.5 • High rated voltage of 5.5V. • High reliability solution leakage. H Max. L Applications B ± 0.2 • Subsidiary power supply. Buck up power supply line. A ± 0.2 Memory backup during battery exchange.
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FC0H473ZFTBR24
FC0H104ZFTBR24
FC0H224ZFTBR24
FC0V104ZFTBR24
FC0V224ZFTBR24
FC0V474ZFTBR24
FC0V683ZFTBR16
FC0H474ZFTBR32
FC0H105ZFTBR44
L5-001
tokin 0.47f 5.5v
NEC tokin 0,22F
tokin 108
tokin 473
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY AMDH Am79C901 HomePHY Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS Fully in tegrated 1 M bps H om ePNA Physical Layer PHY as defined by Hom e Phoneline N etw orking A llian ce (H om ePN A ) s p ecificatio n 1.1 — Optimized for home networking applications
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OCR Scan
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Am79C901
10BASE-T
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