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    TAG J3 Search Results

    TAG J3 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LXMSJZNCMH-225 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd
    LXMS21NCMH-230 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd
    6178S20P Renesas Electronics Corporation 4K X 4 CACHE TAG RAM Visit Renesas Electronics Corporation
    71215S10PF8 Renesas Electronics Corporation 16K X 15 CACHE BICMOS Cache-Tag SRAM Visit Renesas Electronics Corporation
    71215S9PF Renesas Electronics Corporation 16K X 15 CACHE BICMOS Cache-Tag SRAM Visit Renesas Electronics Corporation

    TAG J3 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    84118 latch

    Abstract: No abstract text available
    Text: GS84118T/B 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp FEATURES • 3.3V +10%/-5% Core power supply, 2.5V or 3.3V I/O supply. • Intergrated data comparator for Tag RAM application. • FT mode pin for FLOW THROUGH or PIPELINE operation.


    Original     		PDF GS84118T/B 100-lead GS84118T- 100-pin GS84118B- 119-ball GS84118-2000207; 84118 latch

    j182

    Abstract: TSSOP10 J196 Transistor J182 if uhf modulator ATA5590 915 MHz RFID j182 transistor j191 chip antenna rfid UHF
    Text: Antenna Matching for UHF – RFID Transponder ICs Overview To achieve high performance with regards to the read and write distance of a tag, it is essential that the tag–antenna design be matched to the ATA5590 input impedance, because the return link modulation of the ATA5590 uses PSK Phase Shift Keying .


    Original     		PDF ATA5590 j182 TSSOP10 J196 Transistor J182 if uhf modulator 915 MHz RFID j182 transistor j191 chip antenna rfid UHF

    B1-66

    Abstract: No abstract text available
    Text: GS84118T/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application


    Original     		PDF GS84118T/B-166/150/133/100 B1-66

    GS84118-2000207

    Abstract: DQ116
    Text: GS84118T/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Intergrated data comparator for Tag RAM application


    Original     		PDF GS84118T/B-166/150/133/100 GS84118-2000207 DQ116

    SiS 651 chipset

    Abstract: SiS chipset TI HA04 logic diagram of 74LS245 SIS 651 128m simm 72 pin ide hardisk sis chipset ide pci to isa bridge Silicon Integrated System
    Text: SiS5120 Pentium PCI/ISA Chipset 1. Introduction PBSRAM CPU Host Address Host Data Bus Tag RAM MD Bus 244 x 2 optional MA Bus Master IDE DRAM SiS5120 USB GPIO BIOS KBC 245 x2 or x4 PCI Bus ISA Bus ISA Device ISA Device ISA Device ISA Dev ice PCI Device PCI


    Original     		PDF SiS5120 SiS 651 chipset SiS chipset TI HA04 logic diagram of 74LS245 SIS 651 128m simm 72 pin ide hardisk sis chipset ide pci to isa bridge Silicon Integrated System

    "snoop filter"

    Abstract: 82801DB E8870DH E8870SP snoop filter ITANIUM2 82870P2 E8870 E8870IO P64H2
    Text: Intel E8870SP Scalability Port Switch SPS Datasheet Product Features • ■ ■ Scalability Port (SP): — Six SPs with 3.2 GB/s peak bandwidth per direction per SP. — Bi-directional SPs for a total bandwidth of 38.4 GB/s. Integrated Snoop Filter: — 1 MB 12-way set associative tag array


    Original     		PDF E8870SP 12-way "snoop filter" 82801DB E8870DH snoop filter ITANIUM2 82870P2 E8870 E8870IO P64H2

    RAS 1210 SUN HOLD

    Abstract: sun hold ras 1210 SiS5571 magnetic switch diagram push botton SiS chipset IRQ1-15 t85 ha6 HA2311 Silicon Integrated System HA25
    Text: SiS5571 Pentium PCI/ISA Chipset 1. System Block Diagram PBSRAM CPU Host A ddress Host Data Bus Tag RAM MD Bus Master IDE MA Bus SiS5571 Keyboard DRAM USB PCI Bus ISA Bus ISA Device ISA D ev ice ISA Device Preliminary V2.0 December 9, 1996 ISA Device PCI Device


    Original     		PDF SiS5571 75/66/60/50MHz 64-bit 32-bit RAS 1210 SUN HOLD sun hold ras 1210 magnetic switch diagram push botton SiS chipset IRQ1-15 t85 ha6 HA2311 Silicon Integrated System HA25

    TVC501

    Abstract: 011-0049-01 Sony Semiconductor Replacement Handbook 1991 TD3F14A TDS320 c3940 us federal cataloging h6-1 PG506A Gpib to tds 3000 DATA PRECISION 8200 VOLTAGE CALIBRATOR
    Text: Instruction Manual TDS 310, TDS 320 & TDS 350 Two Channel Oscilloscopes 070-8568-04 Use this manual for TDS 310, TDS 320, and TDS 350 oscilloscopes with serial numbers B040100 and above. Instrument Serial Numbers Each instrument manufactured by Tektronix has a serial number on a panel insert or tag, or stamped on the


    Original     		PDF B040100 B010000 E200000 J300000 H700000 TVC501 011-0049-01 Sony Semiconductor Replacement Handbook 1991 TD3F14A TDS320 c3940 us federal cataloging h6-1 PG506A Gpib to tds 3000 DATA PRECISION 8200 VOLTAGE CALIBRATOR

    GS841E18A

    Abstract: T3B5
    Text: GS841E18AT/B-166/150/133/100 166 MHz–100 MHz 8.5 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O 256K x 18 Sync Cache Tag TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply • Dual Cycle Deselect DCD


    Original     		PDF GS841E18AT/B-166/150/133/100 GS841E18AT/B-166/150/130/100 GS841E18A T3B5

    Untitled

    Abstract: No abstract text available
    Text: G MICRO" M ITSUBISHI L S ., .V \\^ Z > M 332 4 3G S -25 ,-3 0 CMOS TAG MEMORY M 32/TAG M DESCRIPTION M 3 3 2 4 3 G S -2 5 , -3 0 (M 3 2 /T A G M ) is 5 1 2 entry X 4 w ay PIN CONFIGURATION (BOTTOM VIEW) /1 0 2 4 entry X 2 w ay T A G M em o ry fa b ric a te d with a C M O S


    OCR Scan     		PDF 32/TAG M33243GS-25

    Untitled

    Abstract: No abstract text available
    Text: G m ic r o " t, 2 * H f l 2 a o a i s i H b . m h M its u b is h i l s i , M33243GS-25,-30 s« * • n iT S U B X S H iin ic n P T R /n iP R O ete d CMOS TAG MEMORY M 32/TA G M r^ z s -s > [ DESCRIPTION M33243GS-25, -30 (M 32/TAG M ) is 512 entry X 4 way


    OCR Scan     		PDF M33243GS-25 32/TA M33243GS-25, 32/TAG

    D425G

    Abstract: ACT21 SN74BCT2166
    Text: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~


    OCR Scan     		PDF SN74BCT2163, SN74BCT2164, SN74BCT2166 SCHS012-D3513, 1990-REVISED BCT2163 BCT2164 BCT2166 D425G ACT21

    SCAD002

    Abstract: BCT2164
    Text: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs _ D3513, JUNE 1990 — REVISED A U G U S T 1990 • Fast Address to MATCH Delay . . .12-ns Max • ’BCT2163 has Totem-Pole Match Output


    OCR Scan     		PDF SN74BCT2163, SN74BCT2164, SN74BCT2166 D3513, 12-ns BCT2163 BCT2164 BCT2166 75-pF SCAD002

    TA114

    Abstract: BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486
    Text: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel


    OCR Scan     		PDF Intel486â lntel486TM TA114 BWEB TA111 PC 2500H SA02 SA07 ta115 485Turbocache 82485M L486

    CSM 6850

    Abstract: mg80960xa 80960XA BV EI 303 3628 80960CA 80960KA 80960KB 80960MC M8259A 77106
    Text: 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY M ilita ry • Implements JIAWG 32-Bit ISA Standard ■ High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at


    OCR Scan     		PDF 80960XA 32-BIT 80-Bit CG/SALE/101789 CSM 6850 mg80960xa 80960XA BV EI 303 3628 80960CA 80960KA 80960KB 80960MC M8259A 77106

    W22C

    Abstract: S12301DS 5133S stp520 t12m256 T12M256A-12J UPC507 MITAC PC515 GP014
    Text: MODEL : 5133S Revision 02A Table of Contents page 1 Cover Sheet Block Diagram 2 Central Processor Unit 3 North Bridge Part A & PBSRAM/TAG RAM 4 North Bridge Part B 5 System Memory 6 South Bridge 7 PCMCIA Controller & Socket 8 Audio Codec & Amplifier 9 Enhance IDE & FDD Connector


    OCR Scan     		PDF 5133S VT82C686A 1000P 2N7002 2N7002 MLL34B SCK431CSK-1 OT23N W22C S12301DS stp520 t12m256 T12M256A-12J UPC507 MITAC PC515 GP014

    8kx1 RAM

    Abstract: SN74BCT216012 D3512 SN74ACT2160 SN74BCT2160-12
    Text: SN74BCT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM SCHS011 - D3512, JUNE 1990- REVISED MARCH 1992 Fast Address to Match Time. . . 12 ns Max IO Upgrade of the SN74ACT2160 FM PACKAGE TOP VIEW o • 't CO OJ 1- o < < < < < < Q 2-Way Architecture Significantly Improves


    OCR Scan     		PDF SN74BCT2160 SCHS011 D3512, SN74ACT2160 FM032 R-PLCC-J32 8kx1 RAM SN74BCT216012 D3512 SN74BCT2160-12

    82485

    Abstract: No abstract text available
    Text: Â M © 1 DGsOF@K[MÄ¥D Kl J n te l DEC 05 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Ì486TM MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag


    OCR Scan     		PDF 486TM 132-Pin 82485

    SiS 301 chipset

    Abstract: opti chipset TAG 503 static ram 64kx8 malaysia microelectronic solution low power asynchronous SRAM 64KX8 3.3V tag 136 m2
    Text: AS7M64U3256A Asvnc AS7M64U3512A Async í c i v u -i i i h - í i AS7M64L!32?6B B urst AS7M64U3512B B urst I l High-Performance 256/M2 KByte 3 .3 \ ^ Cache M odules «• Low Voltage 256/512 KByte Cache M odules with Tag PRELIMINARY ASYNCHRONOUS VERSIONS


    OCR Scan     		PDF 256/M2 AS7M64U3256A AS7M64U3512A AS7M64L AS7M64U3512B D03M4T SiS 301 chipset opti chipset TAG 503 static ram 64kx8 malaysia microelectronic solution low power asynchronous SRAM 64KX8 3.3V tag 136 m2

    82485

    Abstract: EA0S PC 2500H tagram match SA010 SA09 TAI11 "Lookaside Cache"
    Text: » ù n tg l 0 5 ¡991 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Ì 486 TM MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel


    OCR Scan     		PDF 486TM 132-Pin 82485 EA0S PC 2500H tagram match SA010 SA09 TAI11 "Lookaside Cache"

    Untitled

    Abstract: No abstract text available
    Text: m mmRF PraiiiKis m 140 Com m erce Drive M icrosem i Nfontgomeryville, PA 18936-1013 Tel: 215 631-9840 S D 1 4 9 5 RF & MICROWAVE TRANSISTORS 850-890MHz CLASS C, BASE STATIONS « « * , » » « CLASS C TRANSÌSTOR FREQUENCY 870MHz VOL TAG P 24V POWER OUT


    OCR Scan     		PDF 850--890MHz 870MHz 13fc4

    2SC734

    Abstract: 2SA561 2SA5610 2SC734 Y transistor 2SC734 transistor 2SA561 2SA561-Y 2SC734 R
    Text: v 'j3> P N P x f$+ -> r P C m 2SA561 SILICON PNP EPITAXIAL TRANSISTOR (PCT PROCESS) 0 D riv er S tag e A m p lifie r A p p lic atio n s • ¡ S i t E - e - f ; V ceo = —5 0 V (M in .) • ISfQ'SEE^'iS''' : VCE(sat) = —0.3V(M ax.) • 2SC734 i 3 y /. v 9 V K tz 'O


    OCR Scan     		PDF 2SA561 2SC734i 2SC734 150mA 100mA, 2SA561 2SA561â 2SC734 2SA5610 2SC734 Y transistor 2SC734 transistor 2SA561 2SA561-Y 2SC734 R

    Untitled

    Abstract: No abstract text available
    Text: Ä G S M A N G E O M [F iG M T D @ të 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY Military • On-Chip Memory Management Unit — 4 Gigabyte Linear Address Space per Task — 4 Kbyte Pages with Supervisor/User


    OCR Scan     		PDF 80960XA 32-BIT 80-Bit 80960XA

    Untitled

    Abstract: No abstract text available
    Text: Z Z E frO I P S -o n %-n e DAT E DON NO. 26.Jan.2007 062114 REVISED FORM 14.May .2007 062960 REVISED T IT LE REV. 0 N iM V u a - & # ffiH I I DESCRIPTION APPD. &APPD. U E.MATSUMOTO A.ONO0AWA f i ÈÜ CHK. DR. N.SASANO eto. T.TAKESHITA ^^hí&Cé/tAgí^iír A


    OCR Scan     		PDF B5CS03