Untitled
Abstract: No abstract text available
Text: SN74BCT2160 8K X 4 2-WAY CACHE ADDRESS COWIPARATOR/DATA RAM D 3512, JU NE 1990 FM PACKAGE TOP VIEW LO ^ n w r o < < < < < < Fast Address to Match Time . . . 12 ns Max 2-Way Architecture Significantly Improves Hit Rate 4 * Implements LRU Replacement Algorithm
|
OCR Scan
|
SN74BCT2160
T2160
|
PDF
|
SN74BCT2165
Abstract: No abstract text available
Text: SN74BCT2165 8K x 4 2-WAY CACHE ADDRESS COMPARATORS/TAG RAM D 3614, S EPTEM BER 1990 FM P A C K A G E TOP VIEW in n C\j T- o < < < < < < Address to Match Time . . . 12 ns Max Simlar to SN74ACT2160 and SN74BCT2160 but with: - Latches Added - Integrated Invalidation and Read Cicuitry
|
OCR Scan
|
SN74BCT2165
SN74ACT2160
SN74BCT2160
7S265
|
PDF
|
SN74BCT2160
Abstract: No abstract text available
Text: SN74BCT2160 8K X 4 2-WAY CACHE ADD REÍSS COMPARATOR/DATA RAM D 3 5 1 2 , A U G U S T 1990 - R E V IS E D A U G U S T 1990 FM P A C K A G E Fast Address to Match Time . . . 12 ns Max CTOP V IE W in < < 2-Way Architecture Significantly Improves Hit Rate <
|
OCR Scan
|
SN74BCT2160
SCAD002.
|
PDF
|
8kx1 RAM
Abstract: SN74BCT216012 D3512 SN74ACT2160 SN74BCT2160-12
Text: SN74BCT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM SCHS011 - D3512, JUNE 1990- REVISED MARCH 1992 Fast Address to Match Time. . . 12 ns Max IO Upgrade of the SN74ACT2160 FM PACKAGE TOP VIEW o • 't CO OJ 1- o < < < < < < Q 2-Way Architecture Significantly Improves
|
OCR Scan
|
SN74BCT2160
SCHS011
D3512,
SN74ACT2160
FM032
R-PLCC-J32
8kx1 RAM
SN74BCT216012
D3512
SN74BCT2160-12
|
PDF
|
D314
Abstract: SN74ACT2160 SN74BCT2165 SN74BCT2160
Text: SN74BCT2165 8K x 4 2-WAY CACHE ADDRESS COMPARATOR _S C H S 0 1 3 - D3614, APRIL 1991 - REVISED MARCH 1992 • Address to Match Time. . . 12 ns Max • Similar to SN74ACT2160 and SN74BCT2160 but with: - Latches Added - Integrated invalidation and Read
|
OCR Scan
|
SN74BCT2165
D3614,
SN74ACT2160
SN74BCT2160
FM032
R-PLCC-J32
D314
|
PDF
|