Untitled
Abstract: No abstract text available
Text: ss DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP $0^ DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flipflops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac cepted. The logic level of the J and K may be allo
|
OCR Scan
|
T54LS/T74LS113/113A
T54LSXXX
T74SLXXX
T74LSXXX
T74LSUnits
|
PDF
|
Untitled
Abstract: No abstract text available
Text: s G 0 ?E S -T H O n S O N D | 7 ^ 5 ^ 3 7 D 01b 033 3 | LOW POWER SCHOTTKY i T54LSÌ13/113^ T74LS113/113A INTEGRATED CIRCUITS 67C 1 6 1 6 1 D T -*& -o 7 -o 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTIO N The T54LS/T74LS113 /1 13A offers individual J, K,
|
OCR Scan
|
T54LS
T74LS113/113A
T54LS/T74LS113
|
PDF
|
LC-D023
Abstract: No abstract text available
Text: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flip flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac cepted. The logic level of the J and K may be allo
|
OCR Scan
|
T54LS/T74LS113/113A
T54LSXXX
T74SLXXX
T74LSXXX
T74LSXXfied
LC-D023
|
PDF
|