Untitled
Abstract: No abstract text available
Text: ClockWorks SY10EL38/L SY100EL38/L FINAL 5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP DESCRIPTION FEATURES • ■ ■ ■ ■ The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are
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SY10EL38/L
SY100EL38/L
SY10/100EL38/L
SY100EL38ZC
Z20-1
SY100EL38ZCTR
Z20-1)
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Untitled
Abstract: No abstract text available
Text: 5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP DESCRIPTION FEATURES • ■ ■ ■ ■ The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output
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SY10EL38/L
SY100EL38/L
20-pin
Z20-1
SY10/100EL38/L
Z20-1
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Untitled
Abstract: No abstract text available
Text: * 5 V / 3 . 3 V ^2. + 4 /6 C L O C K SYNERGY Clockworks G E N E R A T I O N C H IP SY100EL38/L SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable M aster Reset for synchronization Internal 75KQ input pull-down resistors
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SY100EL38/L
SY10EL38/L
SY10EL38ZC
SY10EL38ZCTR
SY100EL38ZC
100EL38ZCTR
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Untitled
Abstract: No abstract text available
Text: * Clockworks SY10EL38/L SY100EL38/L 5V/3.3V h-2, -h4/6 CLO CK GENERATIO N CHIP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization
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OCR Scan
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SY10EL38/L
SY100EL38/L
20-pin
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Untitled
Abstract: No abstract text available
Text: DESCRIPTION FEATURES • 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KQ input pull-down resistors B BSD protection of 2000V PIN CONFIGURATION/BLOCK DIAGRAM VCC Qo Qo Q? Q? Os Oa V e6 L J LU L il LU CEJ T f_T UG LU 'L l J LüJ
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OCR Scan
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SY10/100EL38
SY10EL38ZC
SY100EL38ZC
Z20-1
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Untitled
Abstract: No abstract text available
Text: * Clockworks SY10EL38/L SY100EL38/L 5V/3.3V ^2, ^4/6 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K fì input pull-down resistors
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OCR Scan
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SY10EL38/L
SY100EL38/L
20-pin
Z20-1
10/100EL38/L
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IRT 1250
Abstract: No abstract text available
Text: * 5V /3 .3 V -^2, +4/6 C L O C K SYNERGY G E N E R A T IO N C H IP S E M IC O N D U C T O R FEATURES • 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75Ki2 input pull-down resistors ■ ESD protection of 2000V
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OCR Scan
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SY100EL38/L
75Ki2
SY10EL38/L
SY10EL382C
SY10EL38ZCTR
SY100EL38ZC
SY100EL38ZCTR
Z20-1
IRT 1250
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Untitled
Abstract: No abstract text available
Text: 5V/3.3V -f-2, -f4/6 CLOCK GENERATION CHIP SYNERGY C s y i o e l m /l SY100EL38/L SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K£2 input pull-down resistors
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OCR Scan
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SY100EL38/L
10/100E
L38/L
SY10EL38/L
SY10EL38ZC
SY10EL38ZCTR
SY100EL38ZC
SY100EL38ZCTR
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Untitled
Abstract: No abstract text available
Text: * Clockworks SY10EL38/L SY100EL38/L 5V/3.3V ^2, ^4/6 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K fì input pull-down resistors
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OCR Scan
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SY10EL38/L
SY100EL38/L
20-pin
Z20-1
10/100EL38/L
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