ZB500
Abstract: "Parity Checker" application of parity checker/generator F100K SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
Text: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13
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J28-1
F24-1
SY100S3
SY100S360JC
SY100S360JCTR
SY100S360
F24-1)
ZB500
"Parity Checker"
application of parity checker/generator
F100K
SY100S360
SY100S360FC
SY100S360JC
SY100S360JCTR
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F100K
Abstract: SY100S360 SY100S360FC SY100S360FCTR SY100S360JC SY100S360JCTR Marking ZB
Text: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each
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SY100S360
SY100S360
M9999-032406
F100K
SY100S360FC
SY100S360FCTR
SY100S360JC
SY100S360JCTR
Marking ZB
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F100K
Abstract: SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
Text: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13
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Original
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PDF
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J28-1
F24-1
SY100S3F24-1
SY100S360JC
SY100S360JCTR
SY100S360
F24-1)
F100K
SY100S360
SY100S360FC
SY100S360JC
SY100S360JCTR
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application of parity checker/generator
Abstract: F100K SY100S360 SY100S360JC SY100S360JCTR
Text: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each
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Original
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PDF
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SY100S360
SY100S360
M9999-042307
application of parity checker/generator
F100K
SY100S360JC
SY100S360JCTR
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Untitled
Abstract: No abstract text available
Text: * SYNERGY SEMICONDUCTOR DUAL PARITY CHECKER/GENERATOR FEATURES SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even
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SY100S360
SY100S360
75Ki2
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Untitled
Abstract: No abstract text available
Text: * SYNERGY DUAL PARITY CH ECKER /G EN ERATO R SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps Iee min. o f-70 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for
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SY100S360
2200ps
SY100S360
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Untitled
Abstract: No abstract text available
Text: * DUAL PARITY CHECKER/GENERATOR SYNERGY SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps min. o f-7 0m A Industry standard 100K ECL levels Iee Extended supply voltage option: V ee = -4 .2V to -5.5V Voltage and temperature compensation for
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SY100S360
2200ps
F100K
24-pin
28-pin
SY100S360
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Untitled
Abstract: No abstract text available
Text: * DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps ■ Iee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V
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SY100S360
2200ps
-70mA
SY100S360
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