SY100S325FC Search Results

SY100S325FC Datasheets (8)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
SY100S325FC		Micrel Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Original	PDF
SY100S325FC		Micrel Semiconductor	Interface, Low-Power Hex TTL-To-TTL Translator		Original	PDF
SY100S325FC		Microchip Technology	Integrated Circuits (ICs) - Logic - Translators, Level Shifters - IC TRNSLTR UNIDIR 24CERPACK		Original	PDF
SY100S325FC		Synergy Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Scan	PDF
SY100S325FC		Synergy Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Scan	PDF
SY100S325FC		Synergy Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Scan	PDF
SY100S325FC		Synergy Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Scan	PDF
SY100S325FCTR		Micrel Semiconductor	LOW-POWER HEX ECL-to-TTL TRANSLATOR		Original	PDF

SY100S325FC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
F100K Abstract: SY100S325 SY100S325FC SY100S325FCTR SY100S325JC Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR Micrel, Inc. DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 3.7ns IEE min. of –37mA TTL outputs Extended supply voltage option: VEE = –4.2V to –5.5V 25% faster than National's 325	Original	SY100S325 F100K 24-pin 28-pin SY100S325 M9999-061306 F100K SY100S325FC SY100S325FCTR SY100S325JC	PDF
SY100S325 Abstract: SY100S325DC SY100S325FC SY100S325JC Text: V LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 S E M IC O N D U C TO R FEATURES DESCRIPTION i Max. propagation delay of 3.7ns I ee min. of -37mA ESD protection of 2000V TTL outputs Extended supply voltage option: — VEE = -4.2V to -5.46V The SY100S325 are hex translators for converting 100K	OCR Scan	SY100S325 of-37mA Fl00K) SY100S325 500il SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC	PDF
F100K Abstract: SY100S325 Text: * LO W -PO W ER HEX ECL-to-TTL TRAN SLA TO R SYNERGY SY100S325 S E M IC O N D U C T O R _ DESCRIPTION FEATURES T he SY 100S 325 are hex tran sla to rs fo r con ve rtin g 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.	OCR Scan	SY100S325 -37mA 75Ki2 F100K) D24-1 SY100S325 SY100S325DC D24-1 SY100S325FC F24-1 F100K	PDF
Untitled Abstract: No abstract text available Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.	OCR Scan	SY100S325 SY100S325 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC J28-1 SY10OS325JCTR	PDF
Untitled Abstract: No abstract text available Text: ^ i.OW-POWER HEX EC!.-lo-TTL TRANSLATOR S YN ER G Y :viooS325 S E M IC O N D U C T O R D ES C R IPTIO N FE A TU R E S • Max. propagation delay of 3.7ns ■ Iee min. of -37m A ■ TTL outputs ■ Extended supply voltage option: Vee = -4.2V to -5.5V ■ 25% faster than National's 325	OCR Scan	SY100S325DC SY100S325FC SY100S325JC SY100S325JCTR D24-1 F24-1 J28-1 J28-1	PDF
F100K Abstract: SY100S325 SY100S325FC SY100S325JC SY100S325JCTR Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR SY100S325 DESCRIPTION FEATURES • Max. propagation delay of 3.7ns ■ IEE min. of –37mA ■ TTL outputs ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ 25% faster than National's 325 ■ Differential inputs with built-in offset	Original	SY100S325 F100K 24-pin 28-pin SY100S325 generaF24-1 SY100S325JC J28-1 SY100S325JCTR F100K SY100S325FC SY100S325JC SY100S325JCTR	PDF
LD523 Abstract: No abstract text available Text: LO W -PO W ER HEX ECL-to-TTL TRANSLATOR SYNERG Y SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Ie e min. o f-37 m A TTL outputs Extended supply voltage option: V ee = -4.2V to -5.5V 25% faster than National's 325 Differential inputs with built-in offset	OCR Scan	SY100S325 018-Mot LD523	PDF
Untitled Abstract: No abstract text available Text: LOW -PO W ER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns T h e S Y 1 0 0 S 3 2 5 a re h e x tra n s la to rs fo r c o n v e rtin g 1 0 0 K E C L lo g ic le v e ls to T T L lo g ic le v e ls . In p u ts ca n be	OCR Scan	SY100S325 SY100S325DC SY100S325FC SY1OOS325JC SY100S325JCTR D24-1 F24-1 J28-1	PDF
Untitled Abstract: No abstract text available Text: V LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Ie e The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.	OCR Scan	SY100S325 SY100S325 75Ki2	PDF
Untitled Abstract: No abstract text available Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 3.7ns The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.	OCR Scan	SY100S325 SY100S325 75Ki2 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC J28-1	PDF
Untitled Abstract: No abstract text available Text: * LOW-POWER HEX ECL-tO-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 3.7ns Iee The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers. An	OCR Scan	SY100S325 SY100S325 75Ki2 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC J28-1	PDF
Untitled Abstract: No abstract text available Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting o r differential receivers. An	OCR Scan	SY100S325 SY100S325 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC J28-1 000102B	PDF
F100K Abstract: SY100S325 SY100S325DC SY100S325FC D2618 Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 S E M IC O N D U C TO R FEATURES DESCRIPTION I Max. propagation delay of 3.7ns I Iee min. of -37m A The S Y 100S 325 are hex tran sla to rs fo r converting 100K ECL logic levels to TTL logic levels. Inputs can be	OCR Scan	SY100S325 -37mA F100K) D24-1 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC F100K SY100S325 D2618	PDF
Untitled Abstract: No abstract text available Text: LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERG Y SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Iee min. o f-37 m A TTL outputs Extended supply voltage option: V ee = -4 .2 V to -5 .5 V 25% faster than National's 325 Differential inputs with built-in offset	OCR Scan	SY100S325 SY100S325 75Ki2	PDF

D2418 Abstract: F100K SY100S325 SY100S325DC SY100S325FC SY100S325JC SY100S325JCTR Text: SYNERGY LOW-POWER HEX ECL-to-TTL TRANSLATOR SEMICONDUCTOR SYNERGY SY100S325 SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES • Max. propagation delay of 3.7ns The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be	Original	SY100S325 SY100S325 SY100S325DC D24-1 SY100S325FC F24-1 SY100S325JC J28-1 D2418 F100K SY100S325DC SY100S325FC SY100S325JC SY100S325JCTR	PDF