SUM18N25-165
Abstract: SUM18N25-165-E3
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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8247
Abstract: AN609 SUM18N25-165 48247
Text: SUM18N25-165_RC Vishay Siliconix R-C Thermal Model Parameters DESCRIPTION The parametric values in the R-C thermal model have been derived using curve-fitting techniques. These techniques are described in "A Simple Method of Generating Thermal Models for a Power MOSFET"[1].
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SUM18N25-165
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19-Oct-07
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Untitled
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Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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SUM18N25-165
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SUM18N25-165-E3
2011/65/EU
2002/95/EC.
2002/95/EC
2011/65/EU.
12-Mar-12
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Untitled
Abstract: No abstract text available
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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SUM18N25-165
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2002/95/EC.
2002/95/EC
2011/65/EU.
JS709A
02-Oct-12
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Abstract: No abstract text available
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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SUM18N25-165
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SUM18N25-165-E3
2002/95/EC.
2002/95/EC
2011/65/EU.
JS709A
02-Oct-12
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Untitled
Abstract: No abstract text available
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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Abstract: No abstract text available
Text: SPICE Device Model SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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40467
Abstract: SUM18N25-165
Text: SUM18N25-165 Vishay Siliconix New Product N-Channel 250-V D-S 175_C MOSFET FEATURES D TrenchFETr Power MOSFET D 175_C Junction Temperature D New Low Thermal Resistance Package PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) ID (A) 250 0.165 @ VGS = 10 V 18 APPLICATIONS
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40467
Abstract: SUM18N25-165
Text: SUM18N25-165 Vishay Siliconix New Product N-Channel 250-V D-S 175_C MOSFET FEATURES D TrenchFETr Power MOSFET D 175_C Junction Temperature D New Low Thermal Resistance Package PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) ID (A) 250 0.165 @ VGS = 10 V 18 APPLICATIONS
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SUM18N25-165
Abstract: SUM18N25-165-E3
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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SUM18N25-165
O-263
SUM18N25-165-E3
18-Jul-08
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Untitled
Abstract: No abstract text available
Text: SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (Ω) ID (A) 250 0.165 at VGS = 10 V 18 • TrenchFET Power MOSFET • 175 °C Junction Temperature • Low Thermal Resistance Package RoHS COMPLIANT
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Original
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SUM18N25-165
O-263
SUM18N25-165-E3
2011/65/EU
2002/95/EC.
2002/95/EC
2011/65/EU.
12-Mar-12
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PDF
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SUM18N25-165
Abstract: No abstract text available
Text: SPICE Device Model SUM18N25-165 Vishay Siliconix N-Channel 250-V D-S 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range
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S-60543Rev.
10-Apr-06
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lfxp2-40e
Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Text: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1
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LD48
LFXP2-17E-5FTN256C
ispLEVER project Navigator route place
LFXP2-5E-5QN
IPUG35
LFXP2-8E
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F10-C2
Abstract: SUM22
Text: HSP43881/883 TM Data Sheet May 1999 FN2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single
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FN2449
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vhdl code for 4 bit ripple carry adder
Abstract: VHDL code for 16 bit ripple carry adder 32 bit carry adder vhdl code vhdl code of ripple carry adder vhdl code for full adder EQCOMP12 32 bit ripple carry adder vhdl code vhdl code comparator
Text: fax id: 6434 Back Efficient Arithmetic Designs With Cypress CPLDs Introduction This application note is intended to provide designers with some insight into efficient means of implementing arithmetic functions in Cypress CPLDs. Additionally this application note
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HSP43168
Abstract: circuit diagram for FIR filter B910
Text: HSP43168/883 TM Data Sheet May 1999 FN3177.3 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR
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multiplier accumulator MAC code verilog
Abstract: multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog
Text: LatticeECP-DSP sysDSP Usage Guide October 2005 Technical Note TN1057 Introduction This technical note discusses how to access the features of the LatticeECP -DSP sysDSP™ Digital Signal Processing Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an example of the
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multiplier accumulator MAC code VHDL algorithm
MULT18X18
ispLEVER project Navigator
b312 diode
SUM30
SUM32
TN1057
vhdl code for floating point subtractor
ieee floating point multiplier verilog
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Untitled
Abstract: No abstract text available
Text: LF43891 9 x 9-b it D igital Filter FEATURES_ □ 30 M H z M axim um Sam pling Rate □ 240 M H z M ultiply-Accumulate Rate □ 8 Filter Cells □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Data □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Coefficients
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SUM25
SUM20
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SUM24
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Text: LF43891 9 x 9-bit Digital Filter D E V IC E S IN C O R P O R A T E D □ □ □ □ 40 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data/Coefficients □ 26-bit Data Outputs □ Shift-and-Add Output Stage for
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MIL-STD-883,
HSP43891
HSP43891/883
84-pin
100-pin
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SUM24
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Untitled
Abstract: No abstract text available
Text: HSP43168/883 Data Sheet May 1999 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR
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HSP43168/883
SUM11
SUM10
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SUM15
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Untitled
Abstract: No abstract text available
Text: HSP43881/883 Data Sheet May 1999 File Num ber 2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implem ent vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded
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HSP43881/883
MIL-STD-883
26-bit
SUM24
100kHz
F10/2,
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Untitled
Abstract: No abstract text available
Text: HSP43891/883 ¡33 Digital Filter Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • 0MHz to 25.6MHz Sample Rate • Eight Filter Cells • 9-Bit Coefficients and Signal Data
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Text: LE43R91 zi;»-«- mm LF43891 9 x 9-bit Digital Filter DEVICES INCORPORATED FEATURES □ □ □ □ DESCRIPTION 40 MHz Maximum Sampling Rate 320 MHz Multiply-AccumulateRate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data □ 8-bit Unsigned or 9-bit Two's
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26-bit
MIL-STD-883,
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SUM19
SUM23
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Abstract: No abstract text available
Text: i l l H A R R IS H S P 4 3 8 8 1 Digital Filter A u gu st 1 9 9 2 Features Description • Eight Filter Cells The HSP43881 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells
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