ATS diagram
Abstract: Am29325
Text: Am29325 32-Bit Floating-Point Processor DISTINCTIVE CHARACTERISTICS • • Single VLSI device perform s high-speed floating-point arithm etic - Floating-point addition, subtraction, and m u ltip lic a tio n in a single clock cycle - In te rn a l a rc h ite c tu re s u p p o rts su m -o f-p ro d u cts,
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Am29325
32-Bit
32-bit,
16-bit
16-bit,
145-term
Am29300
F004650
0S621
ATS diagram
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4bit alu
Abstract: k531 PC10 PC11 TC9321F
Text: TOSHIBA TC9321F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9321F SINGLE CHIP DTS MICROCONTROLLER DTS-10 The TC9321F is a 4bit CMOS microcontroller for single chip digital tuning system with built-in prescaler, PLL. The CPU has 4bit parallel addition/subtraction (Al, SI
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TC9321F
DTS-10)
TC9321F
QFP60-P-1414-0
4bit alu
k531
PC10
PC11
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3606
Abstract: No abstract text available
Text: PRELIMINARY IDT77V400 SWITCHStAR ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP SWITCHING MEMORY FEATURES • Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can be independently chosen for Input and Output ports • Byte Addition or Byte Subtraction for x4/x8 to x l 6/x32
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155Mbps
-330m
155Mbps
24Gbps
32-bit
43MHz
50MHz)
IDT77V400
208-pin
3606
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PDF
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1E20
Abstract: No abstract text available
Text: APPLICATION NOTE H8/300L Series Subtraction of 32-Bit Binary Numbers SUB1 Introduction 1. The software SUB1 subtracts a 32-bit binary number from another 32-bit binary number and places the result (a 32bit binary number) in general-purpose registers. 2. The arguments used with the software SUB1 are unsigned integers.
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H8/300L
32-Bit
32bit
REJ06B0154-0100Z/Rev
1E20
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Untitled
Abstract: No abstract text available
Text: Am25LS15 Am25LS15 Quad Serial Adder/Subtractor DISTINCTIVE CHARACTERISTICS • • Magnitude only addition/subtraction Second sourced by T.l. as Am54LS/74LS385 Four independent adder/subtractors Use with two's complement arithmetic GENERAL DESCRIPTION The Am25LS15 is a serial two's complement adder/
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Am25LS15
Am54LS/74LS385
Am25LS14
Am25LS
Am54LS/74LS
IC000180
03663B
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test bench for 16 bit shifter
Abstract: processor control unit vhdl code download verilog code for floating point unit SUBTRACTION verilog code for 8051 verilog code for floating point multiplication microcontroller using vhdl 80C51 DR8051 vhdl code for 8 bit floating point processor
Text: Floating Point Arithmetic Unit ver 1.30 OVERVIEW DFPAU uses the specialized algorithms to compute arithmetic functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, and change sign of a number. The input numbers
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IEEE-754
32-bit
test bench for 16 bit shifter
processor control unit vhdl code download
verilog code for floating point unit
SUBTRACTION
verilog code for 8051
verilog code for floating point multiplication
microcontroller using vhdl
80C51
DR8051
vhdl code for 8 bit floating point processor
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Am29325
Abstract: fc 4558 AM29C33 FT28 tek 455 manual th02
Text: 40V Am 29C325 2 i C M O S 3 2 -B it Flo atin g-P o int P rocessor > 3 DISTINCTIVE CHARACTERISTICS Single VLSI device perform s high-speed single precision floating-point arithm etic F loating-point addition, subtraction, and m ultiplication in a single clo ck cycle
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Am29C325
32-Bit
32-bit,
16-bit
Am29325
fc 4558
AM29C33
FT28
tek 455 manual
th02
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AD-E0091
Abstract: C945 HD61810
Text: HD61810 d s p The HD61810 is a single-chip general-purpose digital signal processors. High-speed floating-point ALU and MULT are provided internally to per form addition/subtraction and multiplication simultaneously in only one cycle, 250 ns (4 MFLOPS).
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HD61810
HD61810
AD-E0091)
AD-E0091
C945
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1B04 transistor
Abstract: 1B05 F003 F100 F103
Text: APPLICATION NOTE H8/300L Super Low Power Series Subtraction of Multiple-Precision Binary Numbers SUB2 Introduction The software SUB2 subtracts a multiple-precision binary number from another multiple-precision binary number and places the result in the data memory where the minuend was set.
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H8/300L
H8/38024
REJ06B0158-0200/Rev
1B04 transistor
1B05
F003
F100
F103
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PDF
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Am9340
Abstract: AmS340 7400 signetics logical block diagram of 80286 AMG3 820Q FLOATING POINT Co Processor reverse carry addition
Text: 3,2 ' y: Am9340 Four-Bit Arithmetic Logic Unit dncfive Characteristic* P ro v id es addition and subtraction and two lo g ic fu n c tions. Typical add tim e of only 20 n s a nd subtract time of only 25ns for 4 bits. Provision m ade for full lo o k -a h e a d arithm etic ove r 1 6 bit words without additional carry pa cka ge .
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Am9340
16-bit
28-bit
MIL-STD-883
Am9340
AmS340
7400 signetics
logical block diagram of 80286
AMG3
820Q
FLOATING POINT Co Processor
reverse carry addition
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI MICROCOMPUTERS 740 Family Reference Programs 3.9 16-Bit Subtract BCD (1) Description Subtraction of 16-bit BCD data is performed. (2) Explanation The contents of WORK01 +1 and WORK01 are subtracted from the contents of WORK00 +1 and WORK00, respectively, and the results are stored to WORK00 +1 and WORK00, respectively.
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16-Bit
WORK01
WORK01
WORK00
WORK00,
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ph10 led display 16 x 32
Abstract: TM2X opa 6111 LED IR RX MTU428 COUNTER LED bcd
Text: MYSON TECHNOLOGY MTU428 Preliminary 4-Bit Micro-Controller with LCD Driver FEATURES (1) Low power dissipation. (2) Powerful instruction set (148 instructions): • Binary addition, subtraction, BCD adjustment, logical operation in direct addressing mode and index
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MTU428
MTU428
ph10 led display 16 x 32
TM2X
opa 6111
LED IR RX
COUNTER LED bcd
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CSBARBT
Abstract: MC68332 CHIP-SELECT CSBARBT DSA0039265
Text: SECTION 2 NOMENCLATURE The following tables show the nomenclature used in the MC68332 User’s Manual. 2.1 Symbols and Operators Table 2–1 Symbols and Operators Symbol Function + Addition - Subtraction two’s complement or negation * Multiplication /
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MC68332
MC68332
CSBARBT
CHIP-SELECT CSBARBT
DSA0039265
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am29325
Abstract: H-14 AM29325GC WF023740 ScansUX970 TB000640
Text: Am29325 32-Bit Floating-Point Processor • Single VLSI device performs high-speed floating-point arithmetic - Floating-point addition, subtraction, and multiplication in a single clock cycle - Internal architecture supports sum-of-products, Newton-Raphson division
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Am29325
32-Bit
32-bit,
16-bit
WF023790
WF023800
WF023810
16-Bit,
H-14
AM29325GC
WF023740
ScansUX970
TB000640
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE M16C/60 Series and M16C/20 Series General-purpose Program for Subtracting 32 Bits 1. Abstract This program performs a 32-bit unsigned subtraction using registers. This program performs a 32-bit unsigned subtraction between memory locations.
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M16C/60
M16C/20
32-bit
REJ05B0160-0200/Rev
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29C325
Abstract: No abstract text available
Text: Am29C325 CMOS 32-B¡t Floating-Point Processor FINAL DISTINCTIVE CHARACTERISTICS • • Single VLSI device performs high-speed single precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle Internal architecture supports sum-of-products,
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Am29C325
32-bit,
16-bit
Am29325
29C325
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Untitled
Abstract: No abstract text available
Text: Am29C325 C M O S 3 2 -B it F lo a tin g -P o in t P ro ce sso r F IN A L D IS T IN C T IV E C H A R A C T E R IS T IC S • • Single VLSI device pe rfo rm s high-speed singlepre cisio n flo a tin g -p o in t arithm etic F lo a tin g -p o in t add ition, subtraction, and m ultiplicatio n
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Am29C325
32-bit,
16-bit
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Untitled
Abstract: No abstract text available
Text: ATM CELL BASED 8 X 8 NON-BLOCKING SINGLE CHIP ADVANCED INFORMATION IDT77V400 SWITCHING MEMORY Integrated D e v ie TechnoJogy, lie . FEATURES: • Byte Addition or Byte Subtraction fo r x8 to x16/x32 U topia conversion capability • Internal header C yclical R edundancy C he ck CRC and
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IDT77V400
x16/x32
208-pin
PK208-1)
77V400
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001C
Abstract: 1B04 1B05
Text: APPLICATION NOTE H8/300L Series Subtraction of Multiple-Precision BCD Numbers SUBD2 Introduction 1. The software SUBD2 subtracts a multiple-precision binary-coded decimal (BCD) number from another multipleprecision BCD number and places the result in the data memory where the minuend was set.
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H8/300L
REJ06B0164-0100Z/Rev
001C
1B04
1B05
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001C
Abstract: 1B04 1B05
Text: APPLICATION NOTE H8/300L Series Subtraction of Multiple-Precision Binary Numbers SUB2 Introduction 1. The software SUB2 subtracts a multiple-precision binary number from another multiple-precision binary number and places the result in the data memory where the minuend was set.
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H8/300L
REJ06B0158-0100Z/Rev
001C
1B04
1B05
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bin2BCD16
Abstract: bcd binary conversion application note AVR204 binary bcd conversion 0938A-A bcd arithmetic BCD2bin16 binary to bcd conversion 16 bits 16 bit binary bcd conversion bcd adder
Text: AVR204: BCD Arithmetics Features Introduction • Conversion 16 Bits ↔ 5 Digits, This application note lists routines for BCD arithmetics. A listing of all implementations with key performance specifications is given in Table 1. 8 Bits ↔ 2 Digits • 2-Digit Addition and Subtraction
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AVR204:
16-bit
AVR204
bin2BCD16
bcd binary conversion application note
AVR204
binary bcd conversion
0938A-A
bcd arithmetic
BCD2bin16
binary to bcd conversion 16 bits
16 bit binary bcd conversion
bcd adder
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC9321F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9321F SINGLE CHIP DTS MICROCONTROLLER DTS-10 The TC9321F is a 4bit CMOS microcontroller for single chip digital tuning system with built-in prescaler, PLL. The CPU has 4bit parallel addition/subtraction (Al, SI
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TC9321F
DTS-10)
TC9321F
QFP60-P-1414-0
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Untitled
Abstract: No abstract text available
Text: TC93P27F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC93P27F DTS Microcontroller DTS-21 The TC93P27F is a 4-bit CMOS microcontroller for single-chip digital tuning systems, featuring a built-in 230-MHz prescaler, PLL, and LCD drivers. The CPU has 4-bit parallel addition and subtraction
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TC93P27F
DTS-21)
TC93P27F
230-MHz
80-pin,
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LF2249
Abstract: 16 stage pipeline TMC2249 digital mixer
Text: LF2249 LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer 12 x 12-bit Digital Mixer DEVICES INCORPORATED FEATURES DESCRIPTION user control for subtraction of products. The sum of the products can also be internally rounded to 16 bits during the accumulation process.
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LF2249
12-bit
LF2249
12-bit
24-bit
CAS13
16 stage pipeline
TMC2249
digital mixer
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