Untitled
Abstract: No abstract text available
Text: P200 -18/Ud STP210 - 18/Ud STP190 - 18/Ud 210 Watt Maximum Power SOLAR PANEL Features • High conversion efficiency based on leading innovative photovoltaic technologies • High reliability with guaranteed +/-3% power output tolerance, ensuring return on investment
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-18/Ud
STP210
18/Ud
STP190
18/Ud
25-year
IEC61215,
IEC61730,
000W/m2
00W/m2
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stp210n75
Abstract: STP210N75F6 210N75F6
Text: STP210N75F6 N-channel 75 V, 3 mΩ, 120 A TO-220 STripFET VI DeepGATE™ Power MOSFET Features Order code VDSS RDS on max ID STP210N75F6 75 V < 3.7 mΩ 120 A • Low gate charge ■ Very low on-resistance ■ High avalanche ruggedness 3 1 2 TO-220 Application
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STP210N75F6
O-220
O-220
210N75F6
stp210n75
STP210N75F6
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schematic diagram reverse forward motor
Abstract: STB210NF02 STB210NF02-1 STB210NF02T4 STP210NF02
Text: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D²PAK/I²PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE STB210NF02/-1 STP210NF02 • ■ ■ VDSS RDS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) TYPICAL RDS(on) = 0.0026Ω
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STP210NF02
STB210NF02
STB210NF02-1
PAK/TO-220
STB210NF02/-1
O-262
O-263
schematic diagram reverse forward motor
STB210NF02-1
STB210NF02T4
STP210NF02
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STB210NF02
Abstract: STB210NF02-1 STB210NF02T4 STP210NF02 p210n B210NF02
Text: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D²PAK/I²PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE STB210NF02/-1 STP210NF02 • ■ ■ VDSS RDS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) TYPICAL RDS(on) = 0.0026Ω
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STP210NF02
STB210NF02
STB210NF02-1
PAK/TO-220
STB210NF02/-1
O-262
O-263
STB210NF02-1
STB210NF02T4
STP210NF02
p210n
B210NF02
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STB210NF02
Abstract: STB210NF02-1 STB210NF02T4 STP210NF02
Text: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D2PAK/I2PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC • ■ ■ TYPE VDSS R DS on ID PD STB210NF02/-1 STP210NF02 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A 120 A 300 W 300 W
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STP210NF02
STB210NF02
STB210NF02-1
D2PAK/I2PAK/TO-220
STB210NF02/-1
O-262
O-263
STB210NF02-1
STB210NF02T4
STP210NF02
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Untitled
Abstract: No abstract text available
Text: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D PAK/I PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE V DSS R DS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) STB210NF02/-1 STP210NF02 • ■ ■ TYPICAL RDS(on) = 0.0026Ω
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PAK/TO-220
STB210NF02/-1
STP210NF02
STP210NF02
STB210NF02
STB210NF02-1
O-263
O-262
O-220
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STP2014
Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The
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STP2014
STP2014
STP2104
STP2014PQFP
160-Pin
MK48T08-1
EBA11
AmZ8
AD27
AD29
AD30
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STP2013
Abstract: Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44
Text: STP2013PGA-50 July 1997 EMC DATA SHEET Error-Correcting Memory Controller DESCRIPTION The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive interrupts. Satellite state machines are granted execution by the arbiter in response to a buffered request. Stalled
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STP2013PGA-50
STP2013
STP2013PGA
299-Pin
STP2013
Mbus master 250 slave circuit
STP2013PGA-50
m-bus
mbus
STP2011
STP2013PGA50
MAD44
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220v AC voltage stabilizer schematic diagram
Abstract: BA 49182 RJh 3047 rjh 3047 equivalent a1458 opto philips ecg master replacement guide MOSFET, rjh 3077 sc1097 philips ecg semiconductors master replacement guide Electronic ballast 40W using 13005 transistor
Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 2-6 Fiber Optic Connectors and Accessories . . . . . . . . . . . See Page 121 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 10-122 Fiber Optic Cable, Connectors, and Accessories . . . . . . See Pages 118-122
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P390-ND
P465-ND
P466-ND
P467-ND
LNG901CF9
LNG992CFBW
LNG901CFBW
LNG91LCFBW
220v AC voltage stabilizer schematic diagram
BA 49182
RJh 3047
rjh 3047 equivalent
a1458 opto
philips ecg master replacement guide
MOSFET, rjh 3077
sc1097
philips ecg semiconductors master replacement guide
Electronic ballast 40W using 13005 transistor
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TAZ BI-DIR
Abstract: Mbus master 250 slave circuit STP2103 MAD32
Text: S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive inter
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OCR Scan
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STP2013
STP2013
TAZ BI-DIR
Mbus master 250 slave circuit
STP2103
MAD32
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Untitled
Abstract: No abstract text available
Text: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter
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OCR Scan
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STP2014
STP2014
STP2104
STP2014PQFP
160-Pin
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Untitled
Abstract: No abstract text available
Text: S T P 2 Û1 3 P G A -50 S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting M emory Controller D e s c r ip t io n The STP2013 Error-C orrecting M em ory C ontroller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request m asters, w hile m onitoring periodic refresh and VIO preem ptive inter
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OCR Scan
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STP2013
STP201
299-Pin
STP2013
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D37M
Abstract: No abstract text available
Text: STP2013PGA-50 S un M ic r o e l e c t r o n ic s J u ly 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting M em ory Controller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request masters, while m onitoring periodic refresh and VIO preem ptive inter
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OCR Scan
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STP2013PGA-50
STP2013
DR0000000000000000000
SSSSSSS00000000000®
TP2013PG
299-Pin
D37M
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STP2014QFP
Abstract: No abstract text available
Text: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter
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OCR Scan
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STP2014
STP2104
STP2014
TP2014PQ
160-Pin
STP2014QFP
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