ZL50011QCG1
Abstract: GR-1244-CORE MS-026 ZL50011
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack
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Original
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ZL50011
ZL50011/QCC
ZL50011/GDC
ZL50011QCG1
ZL50011GDG2
GR-1244-CORE
ZL50011QCG1
MS-026
ZL50011
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PDF
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ZL50010
Abstract: TFR1M GR-1244-CORE MS-026
Text: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15
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Original
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ZL50010
512-ch
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
ZL50010
TFR1M
GR-1244-CORE
MS-026
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PDF
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GR-1244-CORE
Abstract: MS-026 ZL50011 11CH marking
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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ZL50011
GR-1244-CORE
MS-026
ZL50011
11CH marking
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PDF
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BC1211
Abstract: No abstract text available
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection
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Original
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ZL50012
512-ch
BC1211
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PDF
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GR-1244-CORE
Abstract: MS-026 ZL50010
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
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PDF
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ZL50010QCG1
Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0
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Original
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
ZL50010QCG1
ZL50010GDG2
ZL50010QCG1
GR-1244-CORE
MS-026
ZL50010
32CH1
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PDF
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MS-026
Abstract: ZL50012
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection
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Original
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ZL50012
512-ch
ZL50012/QCC
ZL50012/GDC
MS-026
ZL50012
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PDF
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GR-1244-CORE
Abstract: MS-026 ZL50010 TFPW0
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
TFPW0
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PDF
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Untitled
Abstract: No abstract text available
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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ZL50011
GR-1244-CORE
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PDF
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MS-026
Abstract: ZL50012 philips e3 STO11 ci 116h 4094m
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection
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Original
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ZL50012
512-ch
STi0-15
IEEE-1149
STo0-15
STOHZ0-15
MS-026
ZL50012
philips e3
STO11
ci 116h
4094m
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PDF
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FOX 20.000 MHZ
Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
FOX 20.000 MHZ
LMT 324
slv ca2
GR-1244-CORE
MS-026
ZL50010
STO14
tfk8k
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PDF
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GR-1244-CORE
Abstract: MS-026 ZL50011
Text: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS
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Original
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ZL50011
512-ch
STi0-15
GR-1244-CORE
MS-026
ZL50011
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PDF
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ZL50012QCG1
Abstract: MS-026 ZL50012 STO10
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • April 2006 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection
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Original
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ZL50012
512-ch
ZL50012/QCC
ZL50012/GDC
ZL50012QCG1
ZL50012GDG2
ZL50012QCG1
MS-026
ZL50012
STO10
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PDF
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32.768Mhz oscillator
Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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ZL50011
GR-1244-CORE
32.768Mhz oscillator
FOX 20.000 MHZ
MS-026
ZL50011
tfk8
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PDF
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Untitled
Abstract: No abstract text available
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0
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Original
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ZL50010
STi0-15
ZL50010/GDC
ZL50010QCG1
ZL50010GDG2
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PDF
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GR-1244-CORE
Abstract: MS-026 ZL50011
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
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Original
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ZL50011
GR-1244-CORE
MS-026
ZL50011
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PDF
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MS-026
Abstract: ZL50012 TFPW0 sto8b
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection
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Original
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ZL50012
512-ch
STi0-15
IEEE-1149
STo0-15
STOHZ0-15
MS-026
ZL50012
TFPW0
sto8b
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PDF
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DS5722
Abstract: No abstract text available
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features VDD STi0-15 S/P Converter FPi CKi Input Timing • • 160 Pin LQFP 144 Ball LBGA • • • • Per-channel message mode Per-channel pseudo random bit sequence PRBS pattern generation and bit error detection
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Original
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ZL50012
512-ch
048Mb/s,
096Mb/s
192Mb/s
DS5722
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PDF
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filter FP1P
Abstract: No abstract text available
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
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Original
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ZL50010
GR-1244-CORE
filter FP1P
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PDF
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TDA 2025
Abstract: Z80 CPU PHYSICAL DIMENSIONS LCC tda 2015 Z84C0006CMB TDA 2025 chip z84c0006 cpu Z80 CPU DIMENSIONS centrifuge machine for acceleration 84C0006 zilog z80 dynamic ram Application
Text: ZILOG 9984043 ZILO G INC 03 DËJ 4 0 4 3 03E IN C IL ITA R Y 000044 2 5 | ~ 08442 ¿S, roduct S p ecification l : April 1988 Z84C00 CMOS Z80 CPU Central Processing Unit T - H q - n - o i FEATURES • The CMOS Z80 combines the high performance of the
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OCR Scan
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Z84C00
000fi4b5
40-Pln
Z84C0006CME
Z84C0006CMB
84C00
TDA 2025
Z80 CPU PHYSICAL DIMENSIONS LCC
tda 2015
Z84C0006CMB
TDA 2025 chip
z84c0006 cpu
Z80 CPU DIMENSIONS
centrifuge machine for acceleration
84C0006
zilog z80 dynamic ram Application
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PDF
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