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Catalog Datasheet	Type	Document Tags	PDF
ST10 Abstract: ST10F163 st10 Bootstrap Text: ST10F163 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal RAM Watchdog 16 Interrupt Controller PLL OSC. 16 16 8 Port 6 8 ■ ■ ■ ■ ■ ■ BRG Port 5 6 ASC usart ■	Original	ST10F163 16-BIT 25-MHz ST10 ST10F163 st10 Bootstrap	PDF
st10 Bootstrap Abstract: SKB 7 02 ST10 ST10F163 8051 examples power down SGS-Thomson MCU st10 Text: 7 7 S C S -T H O M S O N “T C «li3 iLi ^[M [¡!l(g§ ST10F163 16-BIT MCU W ITH 128K BYTE FLASH M EM O RY PR ELIM IN A R Y DATA High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits), 800 ns	OCR Scan	ST10F163 16-BIT 25-MHz t-28rd t28wrh st10 Bootstrap SKB 7 02 ST10 ST10F163 8051 examples power down SGS-Thomson MCU st10	PDF
st10 Bootstrap Abstract: partial eras Text: SGS-THOMSON ST10F163 M B M g n [ig m « n S g > 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATASHEET High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits , 800 ns division (32 /1 6 bit)	OCR Scan	ST10F163 16-BIT 25-MHz ST10F163AT1 TQFP100 st10 Bootstrap partial eras	PDF
Untitled Abstract: No abstract text available Text: S G S - T H O M S O N •LitêinMQQeg ST10F163 16-BIT MCU W ITH 128K BYTE FLASH M EM O RY P R ELIM IN A R Y DATA High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication 16 x 16 bits , 800 ns	OCR Scan	ST10F163 16-BIT 25-MHz t28wrh t-28rd	PDF