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    SOFT CORE RTL FIFO Search Results

    SOFT CORE RTL FIFO Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM3HMFYAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFYADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFYAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HNFZAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFZAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFDADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation

    SOFT CORE RTL FIFO Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    slot machine block diagram vhdl

    Abstract: MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom 32Bit verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller
    Text: Inventra MPCI32 Soft Core RTL IP 32bit 33/66MHz PCI Core w/Cardbus support PCI Bus / Cardbus D A T A S H E E T Major Product Features: • Fully compliant with PCI v2.2 specification PCI Core for Peripheral Apps. PCI Bus Interface Target Register Interface


    Original     		PDF MPCI32 32bit 33/66MHz PD-40100 003-FO slot machine block diagram vhdl MPCI32 vhdl code dma controller ,vhdl code for implementation of eeprom verilog code for pci to pci bridge pci verilog code verilog code for EEPROM Controller

    RTL code for ethernet

    Abstract: PE-MCXMAC gmii phy ethernet mac verilog testbench Soft Core RTL FIFO
    Text: A-MCXFIF Inventra™ Soft Core RTL IP FIFO Memory Interface for the PE-MCXMAC™ PEMXCMAC Core A-MXCFIF Core Fabric I/F 32 AMCXTFIF_FAB Fabric Tx Module Generic Synchronous 2 port SRAM Model AMCXTFIF_SYS 32 D A T A S H E E T Major Product Features: GMII


    Original     		PDF PD-59060 001-FO RTL code for ethernet PE-MCXMAC gmii phy ethernet mac verilog testbench Soft Core RTL FIFO

    UTM RESISTOR

    Abstract: MUSBHDRC MUSBHDRC USB2.0 High-Speed Dual-Role Controller verilog code for amba ahb bus verilog code for amba ahb master verilog code AMBA AHB UTM power RESISTOR verilog code for frame synchronization AMBA AHB bus protocol Mentor
    Text: Soft Core RTL IP Inventra MUSBHDRC USB2.0 High-Speed Dual-Role Controller D A T A S Endpoint Control EP0 Control - Host EP0 Control - Function EP1 - 15 Control Combine Endpoints DMA Requests Transmit IN Host Transaction Scheduler Interrupt Control Interrupts


    Original     		PDF 30MHz. PD-40136 002-FO UTM RESISTOR MUSBHDRC MUSBHDRC USB2.0 High-Speed Dual-Role Controller verilog code for amba ahb bus verilog code for amba ahb master verilog code AMBA AHB UTM power RESISTOR verilog code for frame synchronization AMBA AHB bus protocol Mentor

    verilog code for UART baud rate generator

    Abstract: 16550AF verilog code for baud rate generator vhdl code for 8 bit parity generator baud rate generator verilog code for "baud rate" generator address generator logic vhdl code baud rate generator vhdl verilog code for active filter M16550A
    Text: Inventra M16550S Enhanced UART with FIFOs and Synchronous CPU I/F Soft Core RTL IP D A T A S H E E T RCLK RCLK_BAUD BRGE BAUD RATE GENERATOR BAUD Major Product Features: • Software compatible with the NS 16550AF device • Programmable word length, stop bits


    Original     		PDF M16550S 16550AF 16-byte Mode795 PD-40125 002-FO verilog code for UART baud rate generator verilog code for baud rate generator vhdl code for 8 bit parity generator baud rate generator verilog code for "baud rate" generator address generator logic vhdl code baud rate generator vhdl verilog code for active filter M16550A

    verilog code AMBA AHB

    Abstract: MUSBFDRC verilog code for 16 bit ram 40113 Mentor ahb bridge dma controller VERILOG MUSBFSFC RTL 8192
    Text: Inventra MUSBHSFC Soft Core RTL IP USB 2.0 High/Full-Speed Function Controller D DMA Requests Endpoint Control EP0 Control EP1 - 15 Control IN IN MCU Interface OUTIN Interrupt Control Packet Encode/Decode Rx Sync Packet Encode TxRx Macrocell Tx Sync HS Detect


    Original     		PDF 2000/DMA PD-40113 004-FO verilog code AMBA AHB MUSBFDRC verilog code for 16 bit ram 40113 Mentor ahb bridge dma controller VERILOG MUSBFSFC RTL 8192

    MUSBFDRC

    Abstract: verilog code for amba ahb bus Mentor inventra USB Full-Speed Dual-Role Controller "USB" peripheral
    Text: Inventra MUSBFDRC USB Full-Speed Dual-Role Controller Soft Core RTL IP D A T A S H E E T Endpoint Control EP0 Control - Host EP0 Control - Function EP1 - 15 Control DMA Requests Transmit IN Receive IN Host Transaction Scheduler Combine Endpoints CPU Interface


    Original     		PDF PD-40134 005-FO MUSBFDRC verilog code for amba ahb bus Mentor inventra USB Full-Speed Dual-Role Controller "USB" peripheral

    vhdl code for 8 bit ram

    Abstract: MUSBFSFC vhdl synchronous bus
    Text: Inventra MUSBLSFC USB 1.1 Low-Speed Function Controller Soft Core RTL IP D A T A S H E E T Endpoint Control EP0 Control EP1 - 2 Control IN IN OUTIN Combine Endpoints Major Product Features: MCU Interface Interrupt Control Interrupts EP Reg. Decoder Low-speed (1.5 Mbps) functions


    Original     		PDF P1795 PD-40103 002-FO vhdl code for 8 bit ram MUSBFSFC vhdl synchronous bus

    alcatel 1603

    Abstract: No abstract text available
    Text: Inventra Soft Core RTL IP PE-SMII Serial MII I/F for PE-MACMII™ Ethernet MAC Tx Data Tx Data PEMCS Tx Status PETFUN PESMII SMII PHY Rx Data Serial MII Interface Module Rx Data Rx Status A T A S H E E T Major Product Features: PE-MACMII Core HOST D • Works with Alcatel PE-MACMII


    Original     		PDF 10/100Mbps 125MHz modu795 PD-59016 001-FO alcatel 1603

    82c250

    Abstract: MCAN2 40107 BOSCH CAN vhdl bosch can 2.0B BOSCH CAN CONTROLLER vhdl BOSCH CAN Bosch SJA1000 82C250 CAN Driver
    Text: Soft Core RTL IP Inventra MCAN2 CAN 2.0 Network Controller D Transmit Buffer A T A S H E E T Major Product Features: WDATA[7:0] • Supports full CAN 2.0 – both 2.0A (equivalent to CAN 1.2) and 2.0B RDATA[7:0] CPU Interface 64 byte • Supports 11-bit & 29-bit identifiers


    Original     		PDF 11-bit 29-bit 125KBaud 64-byte Listen-Only795 PD-40107 001-FO 82c250 MCAN2 40107 BOSCH CAN vhdl bosch can 2.0B BOSCH CAN CONTROLLER vhdl BOSCH CAN Bosch SJA1000 82C250 CAN Driver

    RMII PHY

    Abstract: 59014 alcatel 1603 rMII verilog 59014 transistor RMII Specification
    Text: Inventra Soft Core RTL IP PE-RMII RMII I/F for PE-MACMII™ 10/100 Ethernet MAC Tx Data Tx Data PEMCS Tx Status PETFUN PERMII Reduced MII Interface Module Rx Data Rx Status Control PECLKRST RMII PHY Tx Control T A S H E E T PEMIIM • Works with Alcatel PE-MACMII


    Original     		PDF 10/100Mbps 50MHz PD-59014 001-FO RMII PHY 59014 alcatel 1603 rMII verilog 59014 transistor RMII Specification

    pci core

    Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
    Text: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration


    Original     		PDF 32-bit 64-bit ASIC-FS-20827-10/99 pci core Soft Core RTL FIFO synchronous fifo design in verilog

    Soft Core RTL USB

    Abstract: microelectronics ASIC USB 2.0 coach 12 Shenzhen State Microelectronics UDC20 RTL 604 GDS VCI
    Text: Standard Bus IP: High Speed USB 2.0 Device Controller Fujitsu Macro F_USB20LP LINK PHY CPU Fujitsu USB 2.0 device controller is a synthesizable core suitable for different process. Corresponding physical interface in 0.18um and 0.11um technology supporting high and full speed operation


    Original     		PDF USB20LP Soft Core RTL USB microelectronics ASIC USB 2.0 coach 12 Shenzhen State Microelectronics UDC20 RTL 604 GDS VCI

    RTL 204 601

    Abstract: 400x240 conector RJ catalog ShMM-1500R leon3 VME64 alma 8051s CZ80CPU A24D16 RT MIL-STD-1553B ACTEL FPGA
    Text: Solutions and IP Catalog Improve Time-to-Market and Reduce Risk March 2010 Table of Contents Introduction 3 Power Management Solutions Mixed-Signal Power Manager MPM 4 System Management Solutions Pigeon Point Systems 5 Motor Control Solutions 6 Display Solutions


    Original     		PDF Core8051s Core10/100 Core429 Core1553BRM Core1553BRT Core1553BRT-EBR Core1553BBC CoreAES128 RTL 204 601 400x240 conector RJ catalog ShMM-1500R leon3 VME64 alma 8051s CZ80CPU A24D16 RT MIL-STD-1553B ACTEL FPGA

    verilog code for slave SPI with FPGA

    Abstract: EP1C3T100C8 vhdl spi interface vhdl spi bus VHDL code for slave SPI with FPGA "Serial peripheral interface" vhdl synchronous bus vhdl code for 8 bit shift register verilog code for 64 32 bit register
    Text: SPI_MS Serial Peripheral Interface Master/Slave Altera Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either


    Original     		PDF

    verilog code for slave SPI with FPGA

    Abstract: vhdl spi interface VHDL code for slave SPI with FPGA
    Text: SPI_MS Serial Peripheral Interface Master/Slave Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either


    Original     		PDF

    100-BASE-FX

    Abstract: 10BASE5 10Base-2 802.3 fx
    Text: 10/100 Mbps Ethernet MAC Core MAC Tx FIFO Transmit Block Core Block Diagram DII Flow Control Address Recognition Logic ▼ CSR Interface Command and Status Registers Receive Block MAC Rx FIFO Features • DMA Independent Interface DII for generic interface to


    Original     		PDF ASIC-FS-20814-10/99 100-BASE-FX 10BASE5 10Base-2 802.3 fx

    verilog code for apb

    Abstract: verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb
    Text: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Core o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample


    Original     		PDF 192kHz 98MHz verilog code for apb verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb

    16550A serial communication

    Abstract: 16550A UART texas instruments datasheet of 16450 UART 16450 UART 16550A UART H16550S
    Text: Capable of running all existing 16450 and 16550a software H16550S Fully Synchronous design. All inputs and outputs are based on rising edge of clock UART with FIFOs and Synchronous CPU Interface Core In FIFO mode, the transmitter and receiver are each buffered


    Original     		PDF 16550a H16550S H16550S 16450-compatible 16550compatible 16550A serial communication 16550A UART texas instruments datasheet of 16450 UART 16450 UART 16550A UART

    16550A serial communication

    Abstract: 16450 16550A H16550S LFX125EB-3 17e7
    Text: H16550S UART with FIFOs and Synchronous CPU Interface Core The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial


    Original     		PDF H16550S 16450-compatible 16550compatible 16550A serial communication 16450 16550A LFX125EB-3 17e7

    verilog code for phy interface

    Abstract: 64Byte UDC20 usb interface engine UDC-20
    Text: USB 2.0 Device Controller Macro Fujitsu Macro F_USB20LP_03 LINK PHY CPU RAM ROM Local CPU Bus 32bit Control Status Register Interrupt Local Bus Interface Internal Bus UTMI Protocol Engine (UDC-20) PHY USB End-Point FIFO ▲ Features • Full compliance with USB 2.0 Device Controller


    Original     		PDF USB20LP 32bit) UDC-20) 480Mbps) 12Mbps) ASIC-FS-20919-3/2002 verilog code for phy interface 64Byte UDC20 usb interface engine UDC-20

    PCA82C250T

    Abstract: Bosch bosch can 2.0B LFX1200B-5
    Text: Implementation of the Basic CAN specification CAN Bus Controller Core No generated Overload Frames Receiving and transmitting of both identifiers CAN specification 2.0B Programmable data rate up to 1 mbps Programmable baud rate prescaler (up to 1/30) Application specific interface to


    Original     		PDF PCA82C250T LFEC20E-5² LFXP2-17E-7² LCMXO2280C-5¹ LFXP10-C-5¹ LFE2-50-7¹ LFSC3GA25-7¹ Bosch bosch can 2.0B LFX1200B-5

    Soft Core RTL USB

    Abstract: "Single-Port RAM" USB 3.0 device USB Controller USB 1.0 specification requirements usb 3.0 LFPS verilog code for amba ahb master "USB" peripheral
    Text:  32-bit OCP Slave interface implemented as a basic microprocessor interface USB3-DEV USB 3.0 SuperSpeed Device Controller IP Core This IP core implements a device controller that conforms to the USB 3.0 SuperSpeed specification. SuperSpeed 3.0 USB enables data transfers up to 5 Gbps while also reducing power


    Original     		PDF 32-bit Soft Core RTL USB "Single-Port RAM" USB 3.0 device USB Controller USB 1.0 specification requirements usb 3.0 LFPS verilog code for amba ahb master "USB" peripheral

    CUSB2

    Abstract: ISP1501
    Text: Full compliance with the USB 2.0 specification CUSB2 USB 2.0 Device Controller Core Control endpoint 0 — fixed 64 Bytes size Configurable for up to 15 IN and 15 OUT endpoints Configurable/programmable number and size of endpoints Configurable/programmable


    Original     		PDF LFX500C-4 CUSB2 ISP1501

    ISERDES2

    Abstract: spartan hdmi oserdes2 oserdes2 DDR spartan6 TMDS33 HDMI verilog code Spartan-6 FPGA DCM_CLKGEN XAPP495 tmds fpga XAPP460
    Text: Application Note: Spartan-6 Family Implementing a TMDS Video Interface in the Spartan-6 FPGA Author: Bob Feng XAPP495 v1.0 December 13, 2010 Summary Transition Minimized Differential Signaling (TMDS) is a standard used for transmitting video data over the Digital Visual Interface (DVI) and High-Definition Multimedia Interface (HDMI).


    Original     		PDF XAPP495 ISERDES2 spartan hdmi oserdes2 oserdes2 DDR spartan6 TMDS33 HDMI verilog code Spartan-6 FPGA DCM_CLKGEN XAPP495 tmds fpga XAPP460