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    Untitled

    Abstract: No abstract text available
    Text: SN74LVC1G132A SINGLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCES137 – JUNE 1998 D EPIC Enhanced-Performance Implanted D D D D DBV OR DCK PACKAGE (TOP VIEW CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN74LVC1G132A SCES137

    Untitled

    Abstract: No abstract text available
    Text: Contents SN74LVC1G00A Page Single 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 LVC Single Gates SN74LVC1G02A Single 2-Input Positive-NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9


    Original     		PDF SN74LVC1G00A SN74LVC1G02A SN74LVC1G04A SN74LVC1G08A SN74LVC1G14A SN74LVC1G32A SN74LVC1G86A SN74LVC1GU04A SN74LVC1G132A

    This single nand gate

    Abstract: No abstract text available
    Text: SN74LVC1G132A SINGLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS S C E S 1 3 7 -J U N E 1998 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C DBV OR DCK PACKAGE


    OCR Scan     		PDF SN74LVC1G132A This single nand gate