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    SN74LV32DR Search Results

    SN74LV32DR Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Type PDF
    SN74LV32DR Texas Instruments Quadruple 2-Input Positive-OR Gate 14-SOIC -40 to 85 Original PDF

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    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS188C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN54LV32 SN74LV32

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN54LV32 SN74LV32

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 SN54LV32 . . . J OR W PACKAGE SN74LV32 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC  (Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND


    Original     		PDF SN54LV32, SN74LV32 SCLS188C SN54LV32

    SN74LV32

    Abstract: SN74LV32D SN74LV32DBLE SN74LV32DR SN74LV32PWLE LV32 SN54LV32
    Text: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN74LV32 SN74LV32D SN74LV32DBLE SN74LV32DR SN74LV32PWLE LV32 SN54LV32

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN54LV32 SN74LV32

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN54LV32 SN74LV32

    Untitled

    Abstract: No abstract text available
    Text: SN54LV32, SN74LV32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS188C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV32, SN74LV32 SCLS188C MIL-STD-883C, JESD-17 300-mil SN54LV32