CONN TRBLK 4
Abstract: C0402X7R100-104K HEADER_1X3
Text: Si 5 3 3 0 1 / 4 - E VB Si53301/4 E VALUATION B OARD U SER ’ S G U ID E Description EVB Features The Si53301/4-EVB is used for evaluation of the Si533xx family of low-jitter clock buffers/level translators. As shipped from the factory, this evaluation board has the Si53301 device installed. The entire
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Si53301/4
Si53301/4-EVB
Si533xx
Si53301
Si53304
CONN TRBLK 4
C0402X7R100-104K
HEADER_1X3
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si514
Abstract: SI510
Text: AN765 T HERMAL A NALYSIS OF S I L I C O N L ABS T I M I N G D EVICES 1. Introduction The junction temperature of semiconductor devices affects reliability and performance of Integrated Circuits ICs , including timing devices. This application note provides the following:
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AN765
si514
SI510
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what is slew rate
Abstract: No abstract text available
Text: AN766 U NDERSTANDING A N D O PTIMIZING C L O C K B UFFER ’ S A D D IT I V E J ITTER P E R F OR MA N C E 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs.
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AN766
what is slew rate
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si5332
Abstract: SMA103A qfn 3X3 land pattern 5310A
Text: Si53322 1:2 L OW - J I T T E R LVPECL C L O C K B UFFER Features 2 LVPECL outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1250 MHz Universal input stage accepts differential or LVCMOS clock VDD: 2.5 / 3.3 V
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Si53322
16-QFN
si5332
SMA103A
qfn 3X3 land pattern
5310A
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Si53308
Abstract: Si533x
Text: Si53308 D U A L 1 : 3 L O W - J I T T E R B UFFER / L EVEL T RANSLATOR Features Ordering Information: See page 28. Storage Telecom Industrial Servers Backplane clock distribution Q2 Q3 Q3 Q4 Q4 26 25 27 28 29 30 Vref Generator DIVA SFOUTA[1] SFOUTA[0]
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Si53308
32-QFN
Si533x
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Untitled
Abstract: No abstract text available
Text: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 29. Applications 34 37 35 36 38 39 40 41 The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable
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Si53302
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Si53304
Abstract: No abstract text available
Text: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz
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Si53304
32-QFN
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Untitled
Abstract: No abstract text available
Text: Si53304 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz
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Si53304
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cross reference guide
Abstract: Silabs SI53302-B-GM
Text: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features 10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable
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Si53302
44-QFN
cross reference guide
Silabs
SI53302-B-GM
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land pattern for TSsOP 16
Abstract: CDCLVC1108 Si53365 si5336
Text: Si53365 1:8 L O W J I T T E R CMOS C LOCK B U FF E R <200 MH Z Features 8 LVCMOS outputs Ultra-low additive jitter: 150 fs rms Wide frequency range: 1 to 200 MHz Asynchronous output enable Low output-output skew: <150 ps
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Si53365
CDCLVC1108
16-TSSOP
land pattern for TSsOP 16
si5336
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Si53314
Abstract: in 5007
Text: Si53314 1 : 6 L O W J IT TE R U N I V E R S A L B U FF E R / L E V E L T R A N S L A T O R W IT H 2 : 1 I N P U T M U X A N D I N D I V I D U A L O E < 1 . 2 5 G H Z Features 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 100 fs rms
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Si53314
32tial
in 5007
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Si53311
Abstract: No abstract text available
Text: S i 5 3 3 11 1:6 L O W J I T T E R U NIVERSAL B UFFER /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX <1.25 GH Z Features Ordering Information: See page 25. Applications Q2 Q3 Q3 Q4 Q4 27 26 25 DIVA 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 22 SFOUTB[0]
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32-QFN
Si53311
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qfn 48 7x7 stencil
Abstract: SI53302-B-GM 53302-B-GM
Text: Si53302 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 25. Applications Q6 Q6 VDDOB 34 37 35 38 39 DIVA 1 33 DIVB SFOUTA[1] SFOUTA[0] 2 32 3 31 SFOUTB[1] SFOUTB[0] Q2 4 Q2 5
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Si53302
44-QFN
qfn 48 7x7 stencil
SI53302-B-GM
53302-B-GM
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Untitled
Abstract: No abstract text available
Text: Si53306 1 : 4 L O W - J ITTER U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN 3 mm x 3 mm
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Si53306
16-QFN
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Si53340-B-GM
Abstract: si53340 SMA103A 5310A
Text: Si53340 1:4 L O W - J I T T E R LV DS C LO C K B U F F E R WITH 2:1 INPUT MUX Features 4 LVDS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1250 MHz 2:1 input mux Universal input stage accepts
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Si53340
16-QFN
Si53340-B-GM
SMA103A
5310A
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536FS
Abstract: No abstract text available
Text: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 28. Storage Telecom Industrial Servers Backplane clock distribution Q3 Q4 Q4 29 28 27 26 25 Functional Block Diagram
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Si53301
32-QFN
536FS
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5310A
Abstract: No abstract text available
Text: Si53323 1:4 L O W - J I T T E R LV PECL C L O C K B U F F E R WI TH 2 : 1 I N P U T M UX Features 4 LVPECL outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1250 MHz 2:1 input mux Universal input stage accepts
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Si53323
16-QFN
5310A
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Si53303
Abstract: No abstract text available
Text: Si53303 D UAL 1:5 L OW J I T T E R B UFFER / L EVEL T RANSLATOR Features 10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable
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Si53303
44-QFN
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qfn 32 land pattern
Abstract: Si53321 si5332 TOP MARK Q8
Text: Si53321 1 : 1 0 L OW J I T T E R LVPECL C LOCK B U F F E R W I T H 2:1 I NPUT M UX < 1.25 GH Z Features Ordering Information: See page 17. Applications High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN)
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Si53321
32-QFN,
32-eLQFP
MC100LVEP111,
CDCLVP111,
MAX9311,
ICS853S111BI,
ICS85310-1
qfn 32 land pattern
si5332
TOP MARK Q8
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si5330
Abstract: No abstract text available
Text: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Ordering Information: See page 24. Applications Q0 Q3 Q3 Q4 Q4 25 1 24 DIVB 2 23 SFOUTB[1] 3 22 SFOUTB[0] 4 GND PAD 5 21 Q5 20 Q5 VDDOB 16 VREF CLK_SEL
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Si53301
32-QFN
si5330
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Si53325
Abstract: si5332
Text: Si53325 D UAL 1:5 L OW J I T T E R LVPECL C LOCK B U F F E R <1.25 GH Z Features Applications Pin Assignments Si53325 Description The Si53325 is an ultra low jitter dual 1:5 LVPECL buffer. The Si53325 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
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Si53325
32-QFN,
32-eLQFP
MC100LVEP210
si5332
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Si53305
Abstract: MO-220 7x7 0.4 pitch SI53305-B-GM
Text: Si53305 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX A N D I NDIVIDUAL OE Features Ordering Information: See page 25. Applications CLK_SEL Q5 Q5 Q6 Q6 VDDOB 34 37 36 35 38 OE7 SFOUT[1] OE2 SFOUT[0] 1 33 2 32 OE1
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Si53305
44-QFN
MO-220 7x7 0.4 pitch
SI53305-B-GM
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Si53320
Abstract: si5332
Text: Si53320 1:5 L O W J I T T E R LVPECL C LOCK B UFFER W I T H 2:1 I NPUT M UX Features 5 LVPECL outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS
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Si53320
20-TSSOP
MC100LVEP14,
SY100EP14U,
MAX9310
si5332
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Untitled
Abstract: No abstract text available
Text: Si53301 1:6 L OW J I T T E R U NIVERSAL B U F F E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX Features Storage Telecom Industrial Servers Backplane clock distribution Q3 Q4 Q4 30 29 28 27 26 25 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 Q0
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Si53301
32-QFN
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