Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SELECTRAM Search Results

    SF Impression Pixel

    SELECTRAM Price and Stock

    Mini-Circuits RAM-6A+

    SMT LNA, DC - 2000 MHZ, 50
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey RAM-6A+ Cut Tape 480 1
    • 1 $9.29
    • 10 $8.845
    • 100 $7.812
    • 1000 $7.16405
    • 10000 $7.16405
    		Buy Now
    Mouser Electronics RAM-6A+ 172
    • 1 $8.42
    • 10 $8.42
    • 100 $7.81
    • 1000 $7.19
    • 10000 $7.19
    		Buy Now

    Taoglas Antenna Solutions FKRAMZPCB

    FAKRA CONNECTOR
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey FKRAMZPCB Bag 100 1
    • 1 $3.13
    • 10 $3.13
    • 100 $2.5
    • 1000 $2.5
    • 10000 $2.5
    		Buy Now

    Taoglas Antenna Solutions FKRAMCPCB

    FAKRA CONNECTOR
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey FKRAMCPCB Bag 100 1
    • 1 $3.13
    • 10 $3.13
    • 100 $2.5
    • 1000 $2.5
    • 10000 $2.5
    		Buy Now

    Cincon Electronics Corporation TR15RAM/30RAM-ASUE

    AC/DC WALL MOUNT ADAPTER
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey TR15RAM/30RAM-ASUE Box 60 1
    • 1 $2.43
    • 10 $2.43
    • 100 $2.43
    • 1000 $2.43
    • 10000 $2.43
    		Buy Now
    Sager TR15RAM/30RAM-ASUE
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    Cincon Electronics Corporation TR15RAM-30RAM-ASUE

    AC/DC WALL MOUNT ADAPTER
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey TR15RAM-30RAM-ASUE Box 60 1
    • 1 $2.43
    • 10 $2.43
    • 100 $2.43
    • 1000 $2.43
    • 10000 $2.43
    		Buy Now
    Find more SELECTRAM price and stock on Findchips.com

    SELECTRAM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XAPP130

    Abstract: verilog code for routing table XCV800 XC4000X XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400
    Text: APPLICATION NOTE  Using the Virtex Block SelectRAM+ XAPP130 October 16, 1998 Version 1.0 13* Advance Application Note Summary The Virtex FPGA Series provides dedicated blocks of on-chip 4096 bit dual-port synchronous RAM. You can use each port of the block SelectRAM+


    Original     		PDF XAPP130 verilog code for routing table XCV800 XC4000X XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400

    DPRAM

    Abstract: XCV600E IMA-32 XC4085XLA
    Text: IMA-32 Inverse Multiplexer for ATM November 15, 1999 Product Specification AllianceCORE Facts Core Specifics 4000XLA 4085XLA09BG352C CLBs/CLB Slices 3136 Clock IOBs 3 IOBs 258 Performance MHz 50 Xilinx Tools M1.5i or later Special Features SelectRAM Supported Family


    Original     		PDF IMA-32 4000XLA 4085XLA09BG352C 4000XLA DPRAM XCV600E XC4085XLA

    testbench verilog for 16 x 8 dualport ram

    Abstract: XAPP131 XAPP205 testbench verilog ram 16 x 4 dual port fifo design code 255x16
    Text: APPLICATION NOTE Data-Width Conversion FIFOs using the Virtex Block SelectRAM Memory R XAPP205, October 25, 1999 Version 1.1 8* Application Note: Nick Camilleri Summary The Virtex FPGA series provides dedicated on-chip blocks of 4096-bit dual-port synchronous RAM (Block SelectRAM+ ).


    Original     		PDF XAPP205, 4096-bit XAPP131 170MHz testbench verilog for 16 x 8 dualport ram XAPP131 XAPP205 testbench verilog ram 16 x 4 dual port fifo design code 255x16

    verilog code 16 bit LFSR

    Abstract: verilog code 8 bit LFSR XAPP131
    Text: 170 MHz FIFOs Using the Virtex Block SelectRAM+  XAPP131 December 10, 1998 Version 1.1 11 Application Note by Nick Camilleri Summary The Virtex FPGA Series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use


    Original     		PDF XAPP131 512x8 170MHz 409other verilog code 16 bit LFSR verilog code 8 bit LFSR

    binary to gray code converter

    Abstract: Logic diagram for asynchronous FIFO circuit for binary to gray code converter 4 bit gray to binary converter circuit block diagram for asynchronous FIFO synchronous fifo asynchronous fifo code in verilog vhdl code for asynchronous fifo synchronous fifo design in verilog vhdl code for a grey-code counter
    Text: Application Note: Virtex Series 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature R XAPP131 v1.3 February 2, 2000 Summary The Virtex FPGA Series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note


    Original     		PDF XAPP131 170MHz xapp131h binary to gray code converter Logic diagram for asynchronous FIFO circuit for binary to gray code converter 4 bit gray to binary converter circuit block diagram for asynchronous FIFO synchronous fifo asynchronous fifo code in verilog vhdl code for asynchronous fifo synchronous fifo design in verilog vhdl code for a grey-code counter

    binary to gray code converter

    Abstract: vhdl code for asynchronous fifo block diagram for asynchronous FIFO asynchronous fifo vhdl 4 bit gray to binary converter circuit 4 bit gray code counter VHDL synchronous fifo 4 bit gray code synchronous counter FIFO error reset full empty synchronous fifo design in verilog
    Text: Application Note: Virtex Series 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature R XAPP131 v1.6 June 5, 2001 Summary The Virtex FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to


    Original     		PDF XAPP131 binary to gray code converter vhdl code for asynchronous fifo block diagram for asynchronous FIFO asynchronous fifo vhdl 4 bit gray to binary converter circuit 4 bit gray code counter VHDL synchronous fifo 4 bit gray code synchronous counter FIFO error reset full empty synchronous fifo design in verilog

    X13002

    Abstract: X13003 XAPP130 x13001 RAM 2816 X130 XC4000X
    Text: Application Note: Virtex Series Using the Virtex Block SelectRAM+ Features R XAPP130 v1.4 December 18, 2000 Summary The Virtex series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can


    Original     		PDF XAPP130 XC4000X 876543210FEDCBA9876543210FEDCBA9876543210 X13002 X13003 XAPP130 x13001 RAM 2816 X130

    x13001

    Abstract: x13003 XAPP130 X130 XC4000X synopsys memory X13002
    Text: Application Note: Virtex Series Using the Virtex Block SelectRAM+ Features R XAPP130 v1.3 March 16, 2000 Summary The Virtex series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can


    Original     		PDF XAPP130 XC4000X 6789ABCDEF0123456789ABCDEF0123456789ABCDE 9876543210FEDCBA9876543210FEDCBA987654321 x13001 x13003 XAPP130 X130 synopsys memory X13002

    XCV150

    Abstract: CY7C1302V25 XAPP133 XAPP214 Xilinx XCV150 xapp214.zip
    Text: Application Note: Virtex Series R XAPP214 v1.0 July 24, 2000 Virtex Device Quad DataRate (QDR) SRAM Interface Author: Tony Williams Summary The Virtex series of FPGAs provides access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip distributed RAM and block SelectRAM+™ features, Virtex


    Original     		PDF XAPP214 CY7C1302V25 XAPP133 xapp214 XCV150 XAPP133 Xilinx XCV150 xapp214.zip

    verilog code for 64 32 bit register

    Abstract: verilog code for 8 bit shift register verilog code for 8 bit fifo register vhdl code for 8 bit shift register vhdl code for 8 bit register vhdl code for shift register using d flipflop vhdl code for 4 bit shift register SRLC64E SRLC32E VHDL of 4-BIT LEFT SHIFT REGISTER
    Text: R Look-Up Tables as Shift Registers SRLUTs Verilog Template // // Module: SelectRAM_16S // // Description: Verilog instantiation template // Distributed SelectRAM // Single Port 16 x 1 // can be used also for RAM16X1S_1 // // Device: Virtex-II Pro Family


    Original     		PDF RAM16X1S h0000; RAM16X1S SRLC16E SRLC16E UG012 verilog code for 64 32 bit register verilog code for 8 bit shift register verilog code for 8 bit fifo register vhdl code for 8 bit shift register vhdl code for 8 bit register vhdl code for shift register using d flipflop vhdl code for 4 bit shift register SRLC64E SRLC32E VHDL of 4-BIT LEFT SHIFT REGISTER

    c405d

    Abstract: No abstract text available
    Text: R Chapter 1 Timing Models Summary The following topics are covered in this chapter: • Processor Block Timing Model • Rocket I/O Timing Model • CLB / Slice Timing Model • Block SelectRAM Timing Model • Embedded Multiplier Timing Model • IOB Timing Model


    Original     		PDF UG012 c405d

    4x4 unsigned multiplier VERILOG coding

    Abstract: vhdl code for lvds driver 32x32 multiplier verilog code MULT18X18 12v relay interface with cpld in vhdl verilog/verilog code for lvds driver 80C31 instruction set vhdl code for 18x18 unSIGNED MULTIPLIER vhdl pulse interval encoder book national semiconductor
    Text: R Chapter 2 Design Considerations Summary This chapter covers the following topics: • • • • • • • • • • • • • • • • • Rocket I/O Transceiver Processor Block Global Clock Networks Digital Clock Managers DCMs Block SelectRAM Memory


    Original     		PDF UG012 4x4 unsigned multiplier VERILOG coding vhdl code for lvds driver 32x32 multiplier verilog code MULT18X18 12v relay interface with cpld in vhdl verilog/verilog code for lvds driver 80C31 instruction set vhdl code for 18x18 unSIGNED MULTIPLIER vhdl pulse interval encoder book national semiconductor

    binary to gray code converter

    Abstract: vhdl code for asynchronous fifo block diagram for asynchronous FIFO testbench verilog ram asynchronous asynchronous fifo vhdl Asynchronous FIFO asynchronous fifo vhdl xilinx xilinx asynchronous fifo vhdl code of binary to gray testbench verilog for 16 x 8 dualport ram
    Text: Application Note: Virtex Series R 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature XAPP131 v1.7 March 26, 2003 Summary The Virtex FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to


    Original     		PDF XAPP131 binary to gray code converter vhdl code for asynchronous fifo block diagram for asynchronous FIFO testbench verilog ram asynchronous asynchronous fifo vhdl Asynchronous FIFO asynchronous fifo vhdl xilinx xilinx asynchronous fifo vhdl code of binary to gray testbench verilog for 16 x 8 dualport ram

    synchronous fifo design in verilog

    Abstract: asynchronous fifo vhdl xilinx vhdl code for asynchronous fifo xilinx asynchronous fifo fifo vhdl xilinx vhdl code for fifo vhdl code for a grey-code counter ram 512x8 8 bit ram using vhdl fifo vhdl
    Text: Application Note: Spartan-II FPGAs R XAPP175 v1.0 November 23, 1999 High Speed FIFOs In Spartan-II FPGAs Application Note Summary This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan -II FPGAs. Verilog and VHDL code is available for the design. The


    Original     		PDF XAPP175 512x8 XC2S15 synchronous fifo design in verilog asynchronous fifo vhdl xilinx vhdl code for asynchronous fifo xilinx asynchronous fifo fifo vhdl xilinx vhdl code for fifo vhdl code for a grey-code counter ram 512x8 8 bit ram using vhdl fifo vhdl

    UG002

    Abstract: CLK180 MC15
    Text: R Chapter 1 Timing Models 1 Summary The following topics are covered in this chapter: • CLB / Slice Timing Model • Block SelectRAM Timing Model • Embedded Multiplier Timing Model • IOB Timing Model • Pin-to-Pin Timing Model • Digital Clock Manager Timing Model


    Original     		PDF UG002 UG002 CLK180 MC15

    verilog code for 16 kb ram

    Abstract: RAMB16s RAMB16 XAPP258 vhdl code for 9 bit parity generator init00
    Text: R Block SelectRAM Memory The DCM_DPS_DFS waveforms in Figure 2-42 shows four DCM outputs namely, clk1x CLK0 output of DCM , clk90 (CLK90 output of DCM), clkfx (CLKFX output of DCM), and clkfx180 (CLKFX180 output of DCM). In this case, the attributes, CLKFX_DIVIDE = 1, and


    Original     		PDF clk90 CLK90 clkfx180 CLKFX180 UG012 verilog code for 16 kb ram RAMB16s RAMB16 XAPP258 vhdl code for 9 bit parity generator init00

    XCS10 vq100

    Abstract: XCS40XL XCS20 pin diagram DS06 XCS05XL XCS10 XCS10XL XCS20 XCS30 PQ208 XCS30
    Text: Spartan and Spartan-XL FPGA Families Data Sheet R DS060 v1.8 June 26, 2008 Introduction Product Specification • System level features - Available in both 5V and 3.3V versions - On-chip SelectRAM memory - Fully PCI compliant - Full readback capability for program verification


    Original     		PDF DS060 XCS30XL CS280 CS144, VQ100 BG256 XCS30 PDN2004-01. XCS10 vq100 XCS40XL XCS20 pin diagram DS06 XCS05XL XCS10 XCS10XL XCS20 XCS30 PQ208

    x13003

    Abstract: XAPP130 X130 XC4000X DI-130 X13002 X000000000
    Text: Application Note: VirtexTM FPGAs XCV series Using the Virtex Block SelectRAM+ Features R XAPP130 (v1.2) December 29, 1999 Application Note Summary The Virtex FPGA Series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the Block SelectRAM+ memory


    Original     		PDF XAPP130 789ABCDEF0123456789ABCDEF0123456789ABCDEF 876543210FEDCBA9876543210FEDCBA9876543210 x13003 XAPP130 X130 XC4000X DI-130 X13002 X000000000

    DS060

    Abstract: No abstract text available
    Text: Product Obsolete/Under Obsolescence Spartan and Spartan-XL FPGA Families Data Sheet R DS060 v2.0 March 1, 2013 Introduction Product Specification • System level features - Available in both 5V and 3.3V versions - On-chip SelectRAM memory - Fully PCI compliant


    Original     		PDF DS060 XCS30XL CS280 CS144, VQ100 BG256 XCS30 PDN2004-01. XCN10016 DS060

    verilog code for 16 bit ram

    Abstract: synchronous fifo design in verilog testbench verilog ram 16 x 4 testbench verilog for 16 x 8 dualport ram XAPP205 XAPP131 testbench vhdl ram 16 x 4 xapp205.zip
    Text: Application Note: Virtex Series Data-Width Conversion FIFOs Using the Virtex Block SelectRAM Memory R Author: Nick Camilleri XAPP205 v1.3 August 10, 2000 Summary Virtex FPGAs provide dedicated on-chip blocks of 4096-bit dual-port synchronous RAM (block SelectRAM+ memory). The block SelectRAM feature is ideal for use in FIFO applications.


    Original     		PDF XAPP205 4096-bit XAPP131 170MHz verilog code for 16 bit ram synchronous fifo design in verilog testbench verilog ram 16 x 4 testbench verilog for 16 x 8 dualport ram XAPP205 XAPP131 testbench vhdl ram 16 x 4 xapp205.zip

    XC4000

    Abstract: XC4003H XC4000A XC4000D XC4000E XC4000EX XC4000H XC4000XL XC5200 XAPP060
    Text: APPLICATION NOTE Design Migration from XC4000 to XC4000E  XAPP 062 October 15,1996 Version1.0 Application Note by Lois Cartier and Marc Baker Summary The XC4000E is an enhanced architecture based on the XC4000 family, but offers many new features, particularly SelectRAMTM memory. When converting XC4000, XC4000A, XC4000D, and XC4000H designs, the XC4000E is an excellent


    Original     		PDF XC4000 XC4000E XC4000E XC4000, XC4000A, XC4000D, XC4000H XC4003H XC4000A XC4000D XC4000EX XC4000XL XC5200 XAPP060

    8 bit data bus using vhdl

    Abstract: XAPP204 vhdl code for memory in cam RAM16x1S 16 word 8 bit ram using vhdl 16 bit register vhdl vhdl code download for memory in cam xapp204.zip XAPP201 XCV100
    Text: Using Block SelectRAM+ for High-Performance Read/Write CAMs  XAPP204 Version 1.1 October 1, 1999 Application Note: Jean-Louis Brelet Summary CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing requirements for data


    Original     		PDF XAPP204 XAPP201, 8 bit data bus using vhdl XAPP204 vhdl code for memory in cam RAM16x1S 16 word 8 bit ram using vhdl 16 bit register vhdl vhdl code download for memory in cam xapp204.zip XAPP201 XCV100

    virtex ucf file 6

    Abstract: V300BG432 "network interface cards" XAPP136
    Text: rm  XAPP136, April 6, 1999 Version 1.1 Synthesizable 143 MHz ZBT* SRAM Interface 13* Application Note by Shekhar Bapat Summary The Virtex Series FPGAs provide access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip SelectRAM and Block


    Original     		PDF XAPP136, virtex ucf file 6 V300BG432 "network interface cards" XAPP136

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X Spartan and S p artan X l Families Field Programmable Gate Arrays September 28, 1998 Version 1.2 Preliminary Product Specification Introduction • System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip SelectRAM memory


    OCR Scan     		PDF SpartaXCS20XL-4 PQ208C PQ208