Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SDR ON FPGA Search Results

    SDR ON FPGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AV-THLIN2BNCM-025 Amphenol Cables on Demand Amphenol AV-THLIN2BNCM-025 Thin-line Coaxial Cable - BNC Male / BNC Male (SDI Compatible) 25ft Datasheet
    CN-DSUB50PIN0-000 Amphenol Cables on Demand Amphenol CN-DSUB50PIN0-000 D-Subminiature (DB50 Male D-Sub) Connector, 50-Position Pin Contacts, Solder-Cup Terminals Datasheet
    CN-DSUBHD62PN-000 Amphenol Cables on Demand Amphenol CN-DSUBHD62PN-000 High-Density D-Subminiature (HD62 Male D-Sub) Connector, 62-Position Pin Contacts, Solder-Cup Terminals Datasheet
    CO-058BNCX200-003 Amphenol Cables on Demand Amphenol CO-058BNCX200-003 BNC Male to BNC Male (RG58) 50 Ohm Coaxial Cable Assembly 3ft Datasheet
    CO-058BNCX200-050 Amphenol Cables on Demand Amphenol CO-058BNCX200-050 BNC Male to BNC Male (RG58) 50 Ohm Coaxial Cable Assembly 50ft Datasheet

    SDR ON FPGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Board Design Guideline

    Abstract: board design guidelines TN-46-06 ddr sdram controller sdr sdram reference EP1S60
    Text: Interfacing DDR SDRAM with Stratix & Stratix GX Devices December 2005 ver. 2.0 Application Note 342 Introduction Traditionally, systems featuring FPGAs used single data rate SDR SDRAM, which transmits data on each rising edge of the clock signal. The total amount of data an SDR memory device can send or receive is equal


    Original     		PDF

    TN1178

    Abstract: DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc
    Text: LatticeECP3 High-Speed I/O Interface June 2010 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one


    Original     		PDF TN1180 TN1178 DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc

    sdram pcb layout guide

    Abstract: vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4
    Text: LatticeECP/EC and LatticeXP DDR Usage Guide February 2007 Technical Note TN1050 Introduction LatticeECP , LatticeEC™ and LatticeXP™ devices support various Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one


    Original     		PDF TN1050 200MHz LatticeEC20 sdram pcb layout guide vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4

    ECP3-150

    Abstract: ddr3 13333mhz LVCMOS15 LVCMOS25 LVCMOS33 SSTL18D
    Text: LatticeECP3 High-Speed I/O Interface November 2009 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one


    Original     		PDF TN1180 ECP3-150 ddr3 13333mhz LVCMOS15 LVCMOS25 LVCMOS33 SSTL18D

    sdr sdram pcb layout guidelines

    Abstract: dqs detect AN2582 DDR2 sdram pcb layout guidelines IPUG35
    Text: LatticeXP2 High-Speed I/O Interface June 2009 Technical Note TN1138 Introduction LatticeXP2 devices support Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock while the DDR interfaces


    Original     		PDF TN1138 RD1019, IPUG35, 1-800-LATTICE sdr sdram pcb layout guidelines dqs detect AN2582 DDR2 sdram pcb layout guidelines IPUG35

    PL12A

    Abstract: 12-8IDDRFXA IPUG35
    Text: LatticeECP2/M High-Speed I/O Interface June 2010 Technical Note TN1105 Introduction LatticeECP2 and LatticeECP2M™ devices support Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock


    Original     		PDF TN1105 166MHz, 200MHz, 266MHz 200MHz PL12A 12-8IDDRFXA IPUG35

    PL12A

    Abstract: QB1E IPUG35
    Text: LatticeECP2/M High-Speed I/O Interface January 2010 Technical Note TN1105 Introduction LatticeECP2 and LatticeECP2M™ devices support Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock


    Original     		PDF TN1105 PL12A QB1E IPUG35

    AN2582

    Abstract: d11 1117 IPUG35
    Text: LatticeXP2 High-Speed I/O Interface June 2010 Technical Note TN1138 Introduction LatticeXP2 devices support Double Data Rate DDR and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock while the DDR interfaces


    Original     		PDF TN1138 166MHz, 200MHz, 266MHz 200MHz AN2582 d11 1117 IPUG35

    software defined radio

    Abstract: functions of multiplier and how it can be developed turbo encoder simulink Turbo Decoder viterbi turbo fec XC2V6000 "channel estimation"
    Text: Perspective Software Defined Radio Virtex-II DSP Engines Enable Software Defined Radio Use Virtex-II FPGAs to create high-performance, flexible SDR systems. by Katie DaCosta DSP Solutions Marketing katie.dacosta@xilinx.com Migrating an existing communication


    Original     		PDF

    JTRS

    Abstract: autocorrelation sdr on fpga memory bandwidth
    Text: USING C-TO-HARDWARE ACCELERATION IN FPGAS FOR WAVEFORM BASEBAND PROCESSING David Lau Altera Corporation, San Jose, CA, dlau@altera.com Jarrod Blackburn, (Altera Corporation, San Jose, CA, jblackbu@altera.com) Charlie Jenkins (Altera Corporation, San Jose, CA, chjenkin@altera.com)


    Original     		PDF

    APP3339

    Abstract: TINIs400 TINI400 XC18V02 sdr03
    Text: Maxim/Dallas > App Notes > MICROCONTROLLERS Keywords: JTAG, FPGA, PROM, SVF file, XILINX devices, TINI, XC18V02 Sep 08, 2004 APPLICATION NOTE 3339 Using the TINI JTAG Library and SVF File to Program Xilinx PROM Devices This application note explains how to use the TINI JTAG library to program Xilinx PROM devices, using a Serial


    Original     		PDF XC18V02 com/an3339 AN3339, APP3339, Appnote3339, APP3339 TINIs400 TINI400 XC18V02 sdr03

    emmc

    Abstract: Core8051 Intelligent Power Module emmc schematic emmc controller emmc ip emmc write emmc firmware Specification eMMC 4.0
    Text: P r o du c t B r i e f MicroTCA Power Module Reference Design Features • Complete MicroTCA Power Module Reference Design – System Management by Actel Fusion MixedSignal FPGA – Compliant to MicroTCA.0 Specification Revision 1.0 – Ready to Plug In for Evaluation and Interoperability Testing


    Original     		PDF

    IPMI BMC

    Abstract: IPMI command format introduction IPMI platform management fru information storage define CORE8051 IPMB IPMI v2.0 BMC IPMI "satellite management controller" AC286 Custom Devices
    Text: Application Note AC286 Actel Fusion FPGAs Supporting Intelligent Peripheral Management Interface IPMI Applications Introduction The IPMI specification includes two elements: 1) a server management protocol and 2) an architectural specification for system management, primarily for server applications. It provides three levels of


    Original     		PDF AC286 IPMI BMC IPMI command format introduction IPMI platform management fru information storage define CORE8051 IPMB IPMI v2.0 BMC IPMI "satellite management controller" AC286 Custom Devices

    APP3339

    Abstract: TINI400 XC18V02 tinis400 AN3339
    Text: Maxim > App Notes > Microcontrollers Keywords: JTAG, FPGA, PROM, SVF file, XILINX devices, TINI, XC18V02 Nov 02, 2004 APPLICATION NOTE 3339 Using the TINI JTAG library and SVF file to program Xilinx PROM devices Abstract: This application note explains how to use the TINI JTAG library to program Xilinx® PROM devices, using a serial


    Original     		PDF XC18V02 com/an3339 AN3339, APP3339, Appnote3339, APP3339 TINI400 XC18V02 tinis400 AN3339

    ISP1507BBSTM

    Abstract: ISP1703 IsP1715 WLCSP25 ISP1507A ISP1715A ISP1508AETTM ISP1507BBS ISP1507ABSTM ISP1105WTS
    Text: USB transceivers Ultra-low-power transceiver solutions for mobile and portable applications October 2009 www.stericsson.com Designed for use with ASICs, FPGAs, and system chipsets that interface with the physical layer of the USB connection, these transceivers provide reliable USB performance in a UTMI+ low pin interface ULPI format and support a full range of mobile and


    Original     		PDF

    abstract on fm modulation and demodulation

    Abstract: CORDIC altera SDR baseband modulation demodulation wifi 5 watt amplifier circuit demodulator fpga fpga based Numerically Controlled Oscillator CORDIC computer smps model wifi antenna hp ipaq
    Text: SYNTHESIZING FPGA CORES FOR SOFTWARE-DEFINED RADIO John Huie General Dynamics Decision Systems, Scottsdale, Arizona, john.huie@gdds.com ; Price D’Antonio (General Dynamics Decision Systems, Scottsdale, Arizona, price.d’antonio@gdds.com); Robert Pelt (Altera Corporation, San


    Original     		PDF pp191-200 abstract on fm modulation and demodulation CORDIC altera SDR baseband modulation demodulation wifi 5 watt amplifier circuit demodulator fpga fpga based Numerically Controlled Oscillator CORDIC computer smps model wifi antenna hp ipaq

    XAPP1064

    Abstract: BUFIO2 ISERDES2 OSERDES iodelay ISERDES spartan 6 serdes oserdes2 DDR spartan6 ISERDES oserdes2
    Text: Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization up to 1050 Mb/s XAPP1064 (v1.1) June 3, 2010 Author: NIck Sawyer Summary Spartan -6 devices contain input SerDes (ISERDES) and output SerDes (OSERDES) blocks. These primitives simplify the design of serializing and deserializing circuits, while allowing


    Original     		PDF XAPP1064 XAPP1064 BUFIO2 ISERDES2 OSERDES iodelay ISERDES spartan 6 serdes oserdes2 DDR spartan6 ISERDES oserdes2

    WLCSP25

    Abstract: ISP1504
    Text: NXP family of ULPI Hi-Speed USB transceivers ISP150x, ISP170x Best-in-class ULPI transceivers for mobile and portable applications Designed for use with ASICs, FPGAs, and system chipsets that interface with the physical layer of the USB connection, these first- and second-generation transceivers provide reliable USB


    Original     		PDF ISP150x, ISP170x WLCSP25 ISP1504

    XAPP972

    Abstract: XCF16P XCF32P XSVF DS123 DS202 MCS-86 Intel MCS-86 interfacing digital batch counter
    Text: Application Note: Platform Flash PROMs R XAPP972 v1.1 February 13, 2009 Updating a Platform Flash PROM Design Revision In-System Using SVF Author: Michol Bauer Summary The Platform Flash XCFP PROM can store multiple design revisions (FPGA bitstreams), of


    Original     		PDF XAPP972 XAPP972 XCF16P XCF32P XSVF DS123 DS202 MCS-86 Intel MCS-86 interfacing digital batch counter

    BittWare

    Abstract: CP-01034-1 adaptive FILTER implementation in c language sdr on fpga software defined radio on fpga fpga based image processing for implementing
    Text: AN FPGA FRAMEWORK SUPPORTING SOFTWARE PROGRAMMABLE RECONFIGURATION AND RAPID DEVELOPMENT OF SDR APPLICATIONS David Rupe BittWare, Concord, NH, USA; drupe@bittware.com ABSTRACT The role of FPGAs in Software Defined Radio (SDR) applications has continued to increase in spite of significant


    Original     		PDF

    VIRTEX-5 xc5vlx50

    Abstract: XCF32P XSVF DS123 DS202 MCS-86 XAPP972 ISC-DISABLE
    Text: Application Note: Platform Flash PROMs R XAPP972 v1.2 September 15, 2009 Updating a Platform Flash PROM Design Revision In-System Using SVF Contact: Randal Kuramoto Summary The Platform Flash XCFP PROM can store multiple design revisions (FPGA bitstreams), of


    Original     		PDF XAPP972 VIRTEX-5 xc5vlx50 XCF32P XSVF DS123 DS202 MCS-86 XAPP972 ISC-DISABLE

    USE OF TRANSISTOR

    Abstract: 2C20 Altera Cyclone II 2C70
    Text: LOW-POWER SOFTWARE-DEFINED RADIO DESIGN USING FPGAS Charlie Jenkins, Altera Corporation San Jose, California, USA; chjenkin@altera.com Paul Ekas, (Altera Corporation San Jose, California, USA; pekas@altera.com) ABSTRACT Software-defined radios (SDR) are emerging as a key


    Original     		PDF 65-nm USE OF TRANSISTOR 2C20 Altera Cyclone II 2C70

    sgmii

    Abstract: mini lvds receiver altLVDS tx 434 TRANSMITTER altera double data rate megafunction sdc
    Text: 6. High-Speed Differential I/O Interfaces and DPA in Stratix V Devices SV51007-1.0 This chapter describes the significant advantages of the high-speed differential I/O interfaces and the dynamic phase aligner DPA over single-ended I/Os and their contribution to the overall system bandwidth achievable with Stratix V FPGAs. All


    Original     		PDF SV51007-1 sgmii mini lvds receiver altLVDS tx 434 TRANSMITTER altera double data rate megafunction sdc

    EP3C120F780

    Abstract: CYCLONE3 IFFT EP3C120 EP3C25
    Text: Part of our Enhanced COTS PLD Initiative Cyclone III FPGAs advancing military and aerospace applications Cyclone III 65-nm FPGAs deliver 1/10th the static power of competing FPGAs and support waveform integration in under 0.2 W Altera Cyclone® III FPGAs are your unparalleled commercial off-the-shelf COTS solution for


    Original     		PDF 65-nm 1/10th SS-01030-1 EP3C120F780 CYCLONE3 IFFT EP3C120 EP3C25