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    SCHEMATIC OF TTL OR GATES Search Results

    SCHEMATIC OF TTL OR GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    GT30J110SRA Toshiba Electronic Devices & Storage Corporation IGBT, 1100 V, 60 A, Built-in Diodes, TO-3P(N) Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    SCHEMATIC OF TTL OR GATES Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    OA41

    Abstract: LO34 on222 transistor VGFX20K lo4b OA43 OAI221 VGFX100K VGFX40K 4 BIT ADDER
    Text: VITESSE FX Family Data Sheet High Performance FX Family Gate Arrays Features • 20,000-350,000 Raw Gates, Channelless Array Architecture • Sea-of-Gates Architecture and Four Layer Metal for High Density • Array Performance - Typical gate delay: 97 ps @ 0.19 mW


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    MIL-STD-883 G51017-0, OA41 LO34 on222 transistor VGFX20K lo4b OA43 OAI221 VGFX100K VGFX40K 4 BIT ADDER PDF

    the peacocks

    Abstract: aa6rv TTL to LVTTL level shifter S1L50282 S1L50000 htri S1L5177 s1l51252
    Text: DATA SHEET ASIC S1L50000 S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V


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    S1L50000 S1L50000 S1L50000H the peacocks aa6rv TTL to LVTTL level shifter S1L50282 htri S1L5177 s1l51252 PDF

    SLA5125

    Abstract: SLA5028 250160 the peacocks Epson Electronics America SLA5668 SLA5506 SLA50000H SLA50000 SLA5075
    Text: DATA SHEET ASIC SLA50000H SLA50000H SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s SLA50000H Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35µm “sea-of-gates” architecture. The SLA50000H products feature 5V


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    SLA50000H SLA50000H SLA5125 SLA5028 250160 the peacocks Epson Electronics America SLA5668 SLA5506 SLA50000 SLA5075 PDF

    RS2-1D7-35

    Abstract: 5vdc relay 12VDC TTL RS2-1D7-33
    Text: Features • • • Compatible with TTL Gates Push−On Connector Terminals Mounts on a TO3 Transistor Heat Sink RS2 Series Printed Circuit Board Mountable Solid State Relay, 7 Amp. D37 1.500 38.1 1.188 (30.2) .325 (8.3) INPUT .670 (17.0) Max OUTPUT .500


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    RS2-1D7-33 RS2-1D7-35 12VDC 15mADC 2500VAC 500VDC) 240VAC RS2-1D7-35 5vdc relay 12VDC TTL RS2-1D7-33 PDF

    Untitled

    Abstract: No abstract text available
    Text: Features • • • Compatible with TTL Gates Push−On Connector Terminals Mounts on a TO3 Transistor Heat Sink RS2 Series Printed Circuit Board Mountable Solid State Relay, 7 Amp. D37 1.500 38.1 1.188 (30.2) .325 (8.3) INPUT .670 (17.0) Max OUTPUT .500


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    12VDC 15mADC 2500VAC 500VDC) 240VAC PDF

    transistor nd8

    Abstract: BT4R ISB28000 bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24
    Text: ISB28000 SERIES HCMOS EMBEDDED ARRAY PRELIMINARY DATA FEATURES Combines Standard Cell features with Sea Of Gates time to market. 0.7 micron triple layer metal HCMOS process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide.


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    ISB28000 transistor nd8 BT4R bt8c pMOS NAND GATE MUX21L AN720 BUT12 BUT18 BUT24 PDF

    MM80C96

    Abstract: MM70C96 MM80C97 C1995 MM70C95 MM70C97 MM70C98 MM80C95 MM80C98 MM80C98N
    Text: MM70C95 MM80C95 MM70C97 MM80C97 TRI-STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI-STATE Hex Inverters General Description Features These gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors The MM70C95 MM80C95


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    MM70C95 MM80C95 MM70C97 MM80C97 MM70C96 MM80C96 MM70C98 MM80C98 MM80C95 MM80C97 C1995 MM80C98 MM80C98N PDF

    XN2222

    Abstract: OA2222L teradyne lasar GLX120K GLX80K 800MHZ GLX15K GLX220K GLX40K ecl nand Logic Family Specifications
    Text: VITESSE Preliminary Data Sheet GLX Family High Performance Low Power GaAs Gate Arrays Features • Sea-of-Gates Core • Low-Power Macros Available • Five Array Sizes: 15K, 40K, 80K, 120K and 220K Raw Gates • Standard TTL, LVTTL, ECL, LVPECL, GTL, HSTL and LVDS I/O Compatibility


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    G52144-0, XN2222 OA2222L teradyne lasar GLX120K GLX80K 800MHZ GLX15K GLX220K GLX40K ecl nand Logic Family Specifications PDF

    CB12000

    Abstract: cd 4847 bt8c dc to ac inverter schematic CB22000 ld3p FD11S FD3S BUT12 BUT18
    Text: CB22000 SERIES HCMOS STANDARD CELL GENERAL DESCRIPTION FEATURES 0.7 micron, double layer metal HCMOS4T process featuring self-aligned twin tub N and P wells, low resistance polysilicide gates and thin metal oxide. 2 - input NAND ND2P delay of 0.30 ns (typ)


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    CB22000 CB12000 cd 4847 bt8c dc to ac inverter schematic ld3p FD11S FD3S BUT12 BUT18 PDF

    dc cdi schematic diagram

    Abstract: Ac cdi schematic diagram California Devices DM30ND cdi schematic level shifter . CMOS to TTL cdi schematic diagram cdi schematics TIL 81 transistor BC 945
    Text: •CALIFORNIA DEVICES INC b4 J CD D e | 1AEST3E 000D334 1 | 3 T-42-11^09 DLM SERIES HCMOS Gate Arrays CALIFORNIA DEVICES INC. April 1985 PRODUCT FEATURES DLM SERIES FAMILY ORGANIZATION • High performance 3 /jm silicon gate HCMOS technology, ■ From 210 to 10,152 equivalent 2-input gates.


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    T-42-11 D-6050 5M85/Prlnted dc cdi schematic diagram Ac cdi schematic diagram California Devices DM30ND cdi schematic level shifter . CMOS to TTL cdi schematic diagram cdi schematics TIL 81 transistor BC 945 PDF

    LBD8

    Abstract: lt08 LT016
    Text: ADV KICRO PLA /P LE /A R R A YS 13E D 1 05S7Sat. Q O a flà lt *1 I Am3530 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS GO 01 Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced


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    05S7Sat. Am3530 24-pin Alb-WCP-15M-9/88 LBD8 lt08 LT016 PDF

    LT016

    Abstract: LT08 YD-350 ecu schematics AIX200 LT08C LBd8 AIX2024 COF2001
    Text: ADV faCRO PLA/PLE/ARRAYS 13E D Am353 b oas?sat, aoaasib 1 1 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced


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    Atn353 24-pin AIS-WCP-15M-9/88-0 LT016 LT08 YD-350 ecu schematics AIX200 LT08C LBd8 AIX2024 COF2001 PDF

    Untitled

    Abstract: No abstract text available
    Text: GATE ARRAYS Features • 0.8nm effective gate lengths 1 .Op.m drawn combined with close metal spacing provides outstanding speed/power performance • Modified channeless architecture provides higher utilization ranging from 2,600 to 130,000 usable gates


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    ATL10 ATL20 ATL60 ATL130 ATL260 PDF

    shiftregisters

    Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
    Text: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock


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    PDF

    ns 4248

    Abstract: Toggle flip flop THREE INPUT TTL OR GATE DUAL FLIP FLOP TRISTATE
    Text: OKI PRELIMINARY SEMICONDUCTOR MSM10V0000 1.5n FLEXIBLE CELL ARRAY FAMILY GENERAL DESCRIPTION FEATURES OKI's Flexible Cell Array FCA "sea-of-gates" series is a high density gate array family which is fabricated using a high performance 1.5^ dual-layer


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    MSM10V0000 ns 4248 Toggle flip flop THREE INPUT TTL OR GATE DUAL FLIP FLOP TRISTATE PDF

    S-MOS navnet

    Abstract: S-MOS asic B16c F1841
    Text: DEC 2 3 i32S _ S-MOS S Y S T E M S • ■ ASIC _ A Seiko Epson Affiliate SLA9000 OCTOBER 1990 HIGH SPEED CMOS GATE ARRAYS DESCRIPTION The S-MOS SLA9000 series is a family of sea-of-gates • 1.0 micron drawn channel length N-Channel


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    SLA9000 SLA9000 S-MOS navnet S-MOS asic B16c F1841 PDF

    MM80C96

    Abstract: MM70C96 MM80C95
    Text: MM70C95/MM80C95, MM70C97/MM80C97 TRI-STATE Hex Buffers MM70C96/MM80C96, MM70C98/MM80C98 TRI-STATE Hex Inverters General Description Features These gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel en­ hancement mode transistors. The MM70C95/MM80C95


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    7/MM80C97/MM70C96/MM80C96/MM70C98/MM80C98 MM70C95/MM80C95, MM70C97/MM80C97 MM70C96/MM80C96, MM70C98/MM80C98 MM70C95/MM80C95 MM70C96/MM80C96 MM70C95/ MM80C96 MM70C96 MM80C95 PDF

    Silicon npn TRANSISTOR TCNL 100

    Abstract: tcnl 100 TRANSISTOR TCNL 100 ECL IC NAND MUX4E schematic of TTL XOR Gates TSN2 tcnl transistor ic xnor XOR23
    Text: T & T MELEC I C b4E D • DOSGQEb OOlGSlfc, Preliminary Data Sheet May 1992 a TG2 ■ ATT? &t M icroelectronics a t BEST-1 Series High-Performance ECL Gate Arrays Features Description ■ 1,000 and 4,000 equivalent logic gates The BEST-1 Series High-Performance ECL Gate


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    005002b 001021b Silicon npn TRANSISTOR TCNL 100 tcnl 100 TRANSISTOR TCNL 100 ECL IC NAND MUX4E schematic of TTL XOR Gates TSN2 tcnl transistor ic xnor XOR23 PDF

    full subtractor using NOR gate for circuit diagram

    Abstract: full subtractor circuit using nor gates AX277 2 bit full adder SIGNAL PATH DESIGNER full subtractor circuit using nand gate
    Text: VITESSE SEMICONDUCT OR 30E D H '1502331 GODDeTb 5 * V T S T -M -H ! Features • VLSI Complexity: > 35,000 Gates •Very Low Power Disspation • Superior Performance: 300M Hz to 3 GHz ■High Yielding, 4 Layer Metal, VLSI Process • Choice of Operating Temperature Ranges:


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    VCB50K Mil-Std-883C, full subtractor using NOR gate for circuit diagram full subtractor circuit using nor gates AX277 2 bit full adder SIGNAL PATH DESIGNER full subtractor circuit using nand gate PDF

    siemens master drive circuit diagram

    Abstract: SR flip flop IC toshiba tc110g TC110G jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
    Text: SIEM EN S ASIC Product Description SCxC1 Family CMOS Gate Arrays FEATURES • Alternate source of Toshiba TC110G family ■ Densities up to 129,000 raw gates ■ Channelless “ sea of gates” architecture ■ 1.5 firn drawn CMOS technology, scalable to 1.0 /¿m


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    TC110G M33S004 siemens master drive circuit diagram SR flip flop IC toshiba tc110g jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram PDF

    Q24060

    Abstract: transistor D1303 m1-6116 Q24008
    Text: ADVANCE DEVICE SPECIFICATION Q24000 SERIES BiCMOS LOGIC ARRAYS DESCRIPTION The AMCC Q24000 Series of BiCM OS logic arrays is comprised of six products with densities of 760, 2160, 5760, 9072, 13,440 and 27,520 equivalent gates. The series is optimized to provide CM OS densities with


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    Q24000 /D1303-0790 Q24060 transistor D1303 m1-6116 Q24008 PDF

    m60013

    Abstract: M60016 m60011 M60014 z46n M60030 M60024 Z24N M60012 m60043
    Text: A m its u b is h i CMOS GATE ARRAYS ELECTRONIC DEVICE GROUP Mitsubishi CMOS Gate Arrays INTRODUCTION Mitsubishi offers three fami­ lies of CMOS gate arrays: 1.0 /im, 1.3 /j.m, and 2.0 ji.m, with usable gates ranging from 200 to 35,000. The 1.0 and 1.3 p.m devices are


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    MDS-GA-11-90-RK m60013 M60016 m60011 M60014 z46n M60030 M60024 Z24N M60012 m60043 PDF

    cq24-000

    Abstract: Q24060 98l18
    Text: Sfe- -<•' m2 DEVICE SPECIFICATION SERIES BiCMOS LOGIC ARRAYS Q24000 DESCRIPTION The AMCC Q24000 Series of BiCMOS logic arrays is comprised of six products with densities ranging from 720 to 13440 equivalent gates including a structured array with a high performance Phase-Locked Loop*.


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    Q24000 Q24000 A7D1320-0892 755-AMCC cq24-000 Q24060 98l18 PDF

    Untitled

    Abstract: No abstract text available
    Text: VITESSE VSC3K/V5C5K/VSC1 OK/ VSG15K/VSC30K High Performance FURY Family Gate Arrays FEATURES • Up to 30,500 Equivalent Gates, Channeled Architecture • Mil-Std-883C, Level B Screening and Qualification Available • ECL and TTL Signal Levels • Commercial, Industrial, Military and


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    Mil-Std-883C, VSG15K/VSC30K TSG2331 0D0103T PDF