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    CDC2509

    Abstract: No abstract text available
    Text: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS58Q - OCTOBER 1996 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs


    OCR Scan     		PDF SCAS58Q CDC2509 24-Pln

    CDC2509

    Abstract: No abstract text available
    Text: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER _SCAS580A - OCTOBER 1996 - REVISED JANUARY 1998 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output


    OCR Scan     		PDF CDC2509 SCAS580A 24-Pin