74AC11648
Abstract: No abstract text available
Text: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths
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Original
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74AC11648
SCAS114
500-mA
300-mil
|
PDF
|
74AC11013
Abstract: No abstract text available
Text: 74AC11013 DUAL 4-INPUT POSITIVE-NAND SCHMITT TRIGGER SCAS112 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity Flow-Through Architecture Optimizes PCB
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Original
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74AC11013
SCAS112
500-mA
300-mil
74AC11013
|
PDF
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Untitled
Abstract: No abstract text available
Text: 74AC11153 DUAL 1ĆOFĆ4 DATA SELECTOR/MULTIPLEXER ą ăą SCAS117A − JUNE 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for
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Original
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74AC11153
SCAS117A
500-mA
300-mil
|
PDF
|
74AC11648
Abstract: No abstract text available
Text: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS ăą SCAS114 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data
|
Original
|
74AC11648
SCAS114
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AC11153 DUAL 1ĆOFĆ4 DATA SELECTOR/MULTIPLEXER ą ăą SCAS117A − JUNE 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for
|
Original
|
74AC11153
SCAS117A
500-mA
300-mil
|
PDF
|
74AC11013
Abstract: No abstract text available
Text: 74AC11013 DUAL 4ĆINPUT POSITIVEĆNAND SCHMITT TRIGGER ą SCAS112 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity Flow-Through Architecture Optimizes PCB
|
Original
|
74AC11013
SCAS112
500-mA
300-mil
74AC11013
|
PDF
|
74AC11648
Abstract: No abstract text available
Text: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS ăą SCAS114 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data
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Original
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74AC11648
SCAS114
500-mA
300-mil
74AC11648
|
PDF
|
74AC11132
Abstract: No abstract text available
Text: 74AC11132 QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT-TRIGGER SCAS113 – D3482, MARCH 1990 – REVISED APRIL 1993 • D OR N PACKAGE TOP VIEW Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Flow-Through Architecture Optimizes
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Original
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74AC11132
SCAS113
D3482,
500-mA
300-mil
74AC11132
|
PDF
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74ACT11648
Abstract: 74ACT11648DW 74ACT11648DWR 74ACT11648NT
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS ą SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data
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Original
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74ACT11648
SCAS115
D3458,
500-mA
74ACT11648
74ACT11648DW
74ACT11648DWR
74ACT11648NT
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PDF
|
Untitled
Abstract: No abstract text available
Text: SN74ACT7801 1024 x 18 CLOCKED FIRSTĆIN, FIRSTĆOUT MEMORY ą SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 • • • • • Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs 1024 Words × 18 Bits Read and Write Operations Can Be
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Original
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SN74ACT7801
SCAS111
D3489,
50-pF
68-Pin
80-Pin
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AC11153 DUAL 1-OF-4 DATA SELECTOR/MULTIPLEXER SCAS117A – JUNE 1990 – REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for
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Original
|
74AC11153
SCAS117A
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 D D D D D D D D SN54ACT16244 . . . WD PACKAGE 74ACT16244 . . . DGG OR DL PACKAGE TOP VIEW Members of the Texas Instruments Widebus Family
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Original
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SN54ACT16244,
74ACT16244
16-BIT
SCAS116B
500-mA
380-mil
25-mil
SN54ACT16244
74pplication
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PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS115 – D3458, MARCH 1990 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data
|
Original
|
74ACT11648
SCAS115
D3458,
500-mA
|
PDF
|
74AC11153
Abstract: 74AC11153D 74AC11153DR 74AC11153N
Text: 74AC11153 DUAL 1ĆOFĆ4 DATA SELECTOR/MULTIPLEXER ą ăą SCAS117A − JUNE 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for
|
Original
|
74AC11153
SCAS117A
500-mA
300-mil
74AC11153
74AC11153D
74AC11153DR
74AC11153N
|
PDF
|
|
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SN74ACT7801
Abstract: No abstract text available
Text: SN74ACT7801 1024 x 18 CLOCKED FIRSTĆIN, FIRSTĆOUT MEMORY ą SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 • • • • • Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs 1024 Words × 18 Bits Read and Write Operations Can Be
|
Original
|
SN74ACT7801
SCAS111
D3489,
50-pF
68-Pin
80-Pin
SN74ACT7801
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS ą SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data
|
Original
|
74ACT11648
SCAS115
D3458,
500-mA
|
PDF
|
74AC11648
Abstract: No abstract text available
Text: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths
|
Original
|
74AC11648
SCAS114
500-mA
300-mil
74AC11648
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AC11153 DUAL 1ĆOFĆ4 DATA SELECTOR/MULTIPLEXER ą ăą SCAS117A − JUNE 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for
|
Original
|
74AC11153
SCAS117A
500-mA
300-mil
|
PDF
|
74AC11013
Abstract: No abstract text available
Text: 74AC11013 DUAL 4ĆINPUT POSITIVEĆNAND SCHMITT TRIGGER ą SCAS112 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity Flow-Through Architecture Optimizes PCB
|
Original
|
74AC11013
SCAS112
500-mA
300-mil
|
PDF
|
74AC11648
Abstract: No abstract text available
Text: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS ăą SCAS114 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data
|
Original
|
74AC11648
SCAS114
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS115- D3456, MARCH 1990-REVISEDAPRIL 1933 Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths
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OCR Scan
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74ACT11648
SCAS115-
D3456,
1990-REVISEDAPRIL
500-mA
|
PDF
|
P3458
Abstract: No abstract text available
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS11 5 - D3458, MARCH 1990-R EV IS ED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses Multiplexed Real-Time and Stored Data
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OCR Scan
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74ACT11648
SCAS11
D3458,
1990-R
500-mA
xas75265
P3458
|
PDF
|
ACT16244
Abstract: 74ACT16244 CT1624
Text: 54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116 - D346S, MARCH 1990 - REVISED APRIL 1993 • Member of the Texas Instruments W idebus Family 54ACT16244 . . . WD PACKAGE 74ACT16244 . . . DGG OR DL PACKAGE • 3-State Outputs Drive Bus Lines or Buffer
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OCR Scan
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54ACT16244,
74ACT16244
16-BIT
SCAS116
D346S,
300-mil
380-mil
25-mil
500-mA
ACT16244
CT1624
|
PDF
|
P34S8
Abstract: 74ACT11648
Text: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS115 - P34S8, MARCH 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses _ J — o — u G [ 1 28 ] C A B Multiplexed Real-Time and Stored Data
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OCR Scan
|
74ACT11648
SCAS115
P34S8,
500-mA
74ACT11648
6Ttil723
texas75265
P34S8
|
PDF
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