Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. BiCMOS StaticRAM 240K 16Kx15-BIT CACHE-TAG RAM For PowerPC and RISC Processors PRELIMINARY IDT71216 This high-speed M A T C H signal, with tADM times as fast as 10ns, provides the fastest possible enabling of secondary
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16Kx15-BIT)
IDT71216
/12ns
4A25771
16KX15
200mV
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Untitled
Abstract: No abstract text available
Text: Æ T 7 S G S -m O M S O N M @i[LI©ir[EMD gS ST9054 32K ROM HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER ADVANCE DATA • Single chip microcontroller with 32K bytes of ROM, 1,280 bytes of static RAM and 256 bytes of register file with 224 general purpose registers
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ST9054
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HLX quartz
Abstract: ST6398 98 UTA ING LA 76811 LM 76811 ST90 xckp CQFP80 PLCC84 PQFP80
Text: 7 7 SGS-THOMSON 'JM, DfflDim@II[L[gOTa@raD g§ ST90158 - ST90135 8/16-BIT MCU FAMILY W ITH 16 to 64K ROM and 512 to 2K RAM P R E L IM IN A R Y D A T A • Register File based 8/16 bit Core Architecture with RUN, W FI, SLOW and HALT modes ■ 0 - 1 6 MHz Operation @ 5V±10%
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ST90158
ST90135
8/16-BIT
250ns
16MHz
16-bit
375ns
6/24/32/48/64K
80-PIN
HLX quartz
ST6398
98 UTA ING
LA 76811
LM 76811
ST90
xckp
CQFP80
PLCC84
PQFP80
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Untitled
Abstract: No abstract text available
Text: In teg rated D evice Technology, Inc. BiCMOS StaticRAM 240K 16Kx15-BIT CACHE-TAG RAM For PowerPC and RISC Processors FEATURES: • 16K x 15 Configuration - 1 2 TAG Bits - 3 Separate I/O Status Bits (Valid, Dirty, Write Through) • Match output uses Valid bit to qualify MATCH output
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16Kx15-BIT)
9/10/12ns
200mV
PN80-1)
2S771
DD2174L
544-SRAM
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mesa
Abstract: No abstract text available
Text: / T T S G S -T H O M S O N ^ 7 # RfflD lM iILI{OT®RQD©i ST90R50 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER ADVANCE DATA • Single chip microcontroller with 256 bytes of reg ister file with 224 general purpose registers avail able as RAM, accumulators or index pointers.
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ST90R50
84-Lead
ST90R50C6
ST90R50C1
24MHz
PLCC84
mesa
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NE 555 SGS
Abstract: S10UT
Text: Æ TTSGS-THOMSON ST90E54 ST90T54 ^7# 32K EPROM HCMOS MCUs WITH BANKSWITCH AND A/D CONVERTER ADVANCE DATA • Single chip m icrocontroller with 32K bytes of EPROM, 1,280 bytes of static RAM and 256 bytes of register file with 224 general purpose registers available as RAM, accum ulators or
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ST90E54
ST90T54
84-Lead
ST90E54L6
ST90E54L1
ST90T54C6
ST90T54C1
24MHz
NE 555 SGS
S10UT
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ST90R50
Abstract: SDM P9
Text: SGS-THOMSON ST90R50 ST90R51 ^ D 0 ^ @ lL i( S ÏÏ^ ( S iQ ( g i ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time : 500ns (12MHz internal) 224 general purpose registers available as RAM,
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ST90R50
ST90R51
500ns
12MHz
16Mbytes
PLCC84
84-pin
ST90R50)
80-pin
ST90R51)
ST90R50
SDM P9
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st90r50
Abstract: No abstract text available
Text: SGS-THOMSON [ M œ [ lL iû r a M O i S T 9 0 R 5 0 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA • Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ■ Minimum instruction cycle time : 500ns (12MHz internal ■ 224 general purpose registers available as RAM,
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500ns
12MHz
16Mbytes
84-pin
ST90R50C)
80-pin
ST90R50Q)
st90r50
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Untitled
Abstract: No abstract text available
Text: S G S -T H O M S O N ST90R52 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER • Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ■ Minimum instruction cycle time: 375ns 16MHz internal ■ 224 general purpose registers available as RAM,
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ST90R52
375ns
16MHz
16Mbytes
PQFP80
80-pin
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Untitled
Abstract: No abstract text available
Text: r z 7 *JÆc S G S -T H O M S O N Mll»[ilL[l irMD gi ST90158 - ST90135 8/16-BIT MCU FAMILY WITH 16 to 64K ROM and 512 to 2K RAM PR ELIM IN A R Y DATA • Register File based 8/16 bit Core Architecture with RUN, W FI, SLOW and HALT modes ■ 0 - 1 6 MHz Operation @ 5V±10%
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ST90158
ST90135
8/16-BIT
250ns
16MHz
16-bit
375ns
16/24/32/48/64K
80-PIN
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ST90R50
Abstract: ST90R50C
Text: Ä 7 # [««LtiOTtëM Oi r Z 7 ST90R50 S G S -T H O M S O N ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA • Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ■ Minimum instruction cycle time : 500ns 12MHz internal ■ 224 general purpose registers available as RAM,
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500ns
12MHz
16Mbytes
84-pin
ST90R50C)
80-pin
ST90R50Q)
PLCC84
ST90R50
ST90R50
ST90R50C
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ST90R50C6
Abstract: st90r50 thomson tv circuit diagram tx 807 st90r 850 va inverter schematic diagram ST90R50C1 st9 technical ST90R50C m 841
Text: Æ 7 S G S -T H O M S O N llD ^I[Ui©inS RDD gi ST90R50 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER ADVANCE DATA • Single chip microcontroller with 256 bytes of reg ister file with 224 general purpose registers avail able as RAM, accumulators or index pointers.
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ST90R50
VA00109
84-Lead
ST90R50C6
ST90R50C1
24MHz
PLCC84
PLCC84
st90r50
thomson tv circuit diagram tx 807
st90r
850 va inverter schematic diagram
st9 technical
ST90R50C
m 841
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