RAPS
Abstract: BS1004A push to make switch red push to make switch o general AC BS10-04A BS1004 Polyamid
Text: RAPS-PUSH BUTTON SWITCH GENERAL ELECTRICAL & MECHANICAL SPECIFICATION Rating: Maintained Rating: Momentary 2 Life: Operating Temperature: Proof voltage: Insulation Resistance: Contact Maintained Contact Momentary (2) Switch Housing: Switch Wafer: Switch Plunger:
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BS1004A
RAPS
BS1004A
push to make switch
red push to make switch
o general AC
BS10-04A
BS1004
Polyamid
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TXC07900AIBG
Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Text: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary
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OED155
TXC-07900
TXC-07900-MB,
OED155TM
TXC07900AIBG
TXC-07900AIBG
TSOP transmitter
B020H
OED155TM
TXC-07900-MB
VTXP-6
AU-AIS
dk12b
EK117
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TranSwitch Corporation
Abstract: B2M1-5
Text: PHAST-1 Device SONET STS-1 Overhead Terminator TXC-06101 DATA SHEET • Provides SONET interface to any type of payload • Programmable STS-1 or STS-N modes • Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for
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TXC-06101
TXC-06101-MB
TranSwitch Corporation
B2M1-5
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TH4B
Abstract: No abstract text available
Text: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis
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TXC-06103
64-byte
TXC-06103-MB
TH4B
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lcsb
Abstract: PM5312 PM5344 PM5345
Text: PM5312 STTX Summary Information SONET/SDH TRANSPORT OVERHEAD TERMINATING TRANSCEIVER FEATURES • Monolithic SONET/SDH Transport Overhead Terminating Transceiver for use in STS-1, STS-3 STM-1 or STS12 (STM-4) applications. • Operates in STS-1 bit serial mode,
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PM5312
STS12
STS-12/
PM5345
S/UNI-155
PM5344
PM5312
PMC-931128
lcsb
PM5344
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TXC-06101AILQ
Abstract: TAIS SOT GR-253-CORE TXC-06101 GR-1400-CORE 1C11C
Text: PHAST-1 Device SONET STS-1 Overhead Terminator TXC-06101 DATA SHEET • Provides SONET interface to any type of payload • Programmable STS-1 or STS-N modes • Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for
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TXC-06101
TXC-06101-MB
TXC-06101AILQ
TAIS SOT
GR-253-CORE
TXC-06101
GR-1400-CORE
1C11C
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HLMP-2500
Abstract: HLMP2450 OPTION S02 HDSP-4830
Text: W K3Ì HEWLETT mLMM PACKARD LED Light Bars Standard Options LIGHT RAPS A N D BAG G ^ A d H ADRA'-' Technical Data O ption S02, S22 D escription Due to applications that require tightly matched devices, HewlettPackard has developed several standard options to service these
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HDSP-4820
HDSP-4830
HDSP-4840
HDSP-4850
HLCP-A100
HLCP-B100
HLCP-C100
HLCP-D100
HLCP-E100
HLCP-F100
HLMP-2500
HLMP2450 OPTION S02
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EW127
Abstract: EWP127A-117W EWP127A EW127A 1127DCT 1127DCM 6150H 1127DEM 35849A PBR120
Text: M ic ro w a v e T ra n s m is s io n L ines 3Ss raps«;, ‘L i * Characteristics Type Numbers Premium Waveguide, Standard Jacket Standard Waveguide, Standard Jacket Premium Waveguide Type CATVP Standard Waveguide, Fire Retardant, Non-Halogenated Jacket 35409-15*
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ns/100
EWP127ool
1127DZ
5849A-1
EW127
EWP127A-117W
EWP127A
EW127A
1127DCT
1127DCM
6150H
1127DEM
35849A
PBR120
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TC528257
Abstract: n724
Text: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The
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TC528257
144WORDS
TC528257
144-w
512-words
TC528257J/SZ/nVTR1017240
TC528257J/SZ/FT/TR-70
TC528257J/SZ/FT/TR-80
n724
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Untitled
Abstract: No abstract text available
Text: SMJ44C250 262 144 BY 4-BIT MULTIPORT VIDEO RAM SGMS037 — JANUARY 1991 * Military Operating Temperature Range JD Package* Top View . . , - 5 5 ° C t o 125°C DRAM: 262 144 Words SAM: 512 Words * * * x x 4 Bits 4 Bits 28 : 27 : 3 26 : SDQ2 TRG c 4 25 :
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SMJ44C250
SGMS037
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SF229
Abstract: toshiba s105
Text: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2M b it C M O S m u ltip o rt m e m o ry eq u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m a ccess m e m o ry R A M p o rt a n d a 5 1 2 -w o rd s by
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TC528257
144WORDS
SF229
toshiba s105
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SRAM timing
Abstract: No abstract text available
Text: SAMSUNG E L E C TRONICS INC b7E J> • 7TbmN2 0Ü177M2 KM79C86 ISfi M S I I S K CMOS SRAM 3 2 K x9 Synchronous Burst Cache RAM with Self-Timed Write FEATURES GENERAL DESCRIPTION • Synchronous Operation The KM79C86 is a 294,912 bit S ynchronou s S tatic Ran
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KM79C86
32Kx9
44-Pin
912xx/
KM79C86
7Tb4142
DD177S1
SRAM timing
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MSM5416263
Abstract: 256x16* STATIC RAM weland SM5416
Text: OKI Semiconductor MSM5416263 262,144-W ord x 1 6 -Bit M ultiport D RA M DESCRIPTION The MSM5416263 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit dynamic RAM and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and asynchronously.
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MSM5416263
144-Word
16-Bit
MSM5416263
512-word
256x16* STATIC RAM
weland
SM5416
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Untitled
Abstract: No abstract text available
Text: H ig h P e rin i 111,1n<c 64K X i A S 7 ' i(S4 M A I CM OS SR\M 64Kx Î2 .Synchronous hursi SH/1M Preliminary information Features • O rg a n iz a tio n : 6 5 ,5 3 6 w o rd s x 32 bits • A sy n c h ro n o u s o u tp u t enable co n tro l • F u lly s y n c h ro n o u s p ip e lin e d o p e ratio n
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AS7C36432
512KB
S7C36432
36432-5Q
36432-STQ
36432-6Q
AS7C36432-6TQ
AS7C36432
36432-7Q
AS7C36432-7TQ
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251S4
Abstract: No abstract text available
Text: SBE C O N N E C T O R S IN S T R U C T IO N S Assembly instructions for S B E * 160 and S B E * 3 2 0 so m » two po*e battery c i onnector with option for two auxiliary contact* S B E * A U X IL IA R Y C O N T A C T S A s s e m b lin g In s tru c tio n s
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251S4
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TLCS-68000
Abstract: No abstract text available
Text: TOSHIBA TMP68000 / 68HC000 5. PROCESSING STATES This section describes the actions of the TM P68000 which are outside the norm al processing associated w ith the execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace
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TMP68000
68HC000
P68000
MPU00-74
TLCS-68000
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Untitled
Abstract: No abstract text available
Text: <991 in te i 80C188XL20,16,12, 10 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of the 80C188 Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O ■ Operation Modes Include: — Enhanced Mode — DRAM Refresh Control Unit
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80C188XL20
16-BIT
80C188
80C188
80C186
80C188XL
PL/M-86,
Pascal-86,
Fortran-86
iC-86
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m514262
Abstract: MSM514262 MSM514262-10 MSM514262-70 MSM514262-80 ZIP28-P-400 M5M51426 MSM51426
Text: O K I Semiconductor MSM5 14262 262,144-Word x 4-Bit Multiport DRAM DESCRIPTION The MSM514262 is a 1-Mbit CMOS m ultiport DRAM com posed of a 262,144-word by 4-bits dynam ic RAM and a 512-words b y 4-bits SAM. Its RAM and SAM operate independently and asynchronously.
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MSM514262
144-Word
MSM514262
512-words
SOJ28-P-400-1
50MBB
SOJ32-P-400-1
m514262
MSM514262-10
MSM514262-70
MSM514262-80
ZIP28-P-400
M5M51426
MSM51426
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Untitled
Abstract: No abstract text available
Text: H ig h P e r f o r m a n c e 64K X 32 C M O S SRA M n II A S7C 36432 6 4 K X 3 2 Synchronous burst SRAM Preliminary information • O r g a n iz a tio n : 6 5 , 5 3 6 w o r d s x 3 2 b its • A s y n c h r o n o u s o u t p u t e n a b le c o n tr o l • F u lly s y n c h r o n o u s p ip e lin e d o p e r a tio n
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c1DD344c
0fic13
S7C36432
AS7C36432
AS7C36432-5QC
AS7C36432-6QC
AS7C36
32-7QC
AS7C36432-STQC
AS7C36432-6TQC
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ha 117324
Abstract: No abstract text available
Text: PRELIMINARY Semiconductor December 1992 NS32 AM 162-20/NS32 AM 163-20 Voice Processor with Serial CODEC Interface General Description The NS32AM162 and the NS32AM163 are integrated 32 bit members of the Series 32000 /EP family of National’s Em bedded System Processors , tuned for the Digital tape
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162-20/NS32
NS32AM162
NS32AM163
ha 117324
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Untitled
Abstract: No abstract text available
Text: IIIIICRTRLY5T • III / Prelim inary S E M I C O N D U C T O R CAT24C02/CAT24C02I 2K-Bit SERIAL E2PROM FEATURES ■ PC Bus C o m p atib le* S e lf Tim ed Prog ram m in g C ycle w ith A u toerase ■ Low Pow er C M O S Tech no log y 100,000 E rase/W rite Cycles
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CAT24C02/CAT24C02I
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Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR DS1306 Serial Alarm Real Tim e C lock RTC FEATURES PIN ASSIGNMENT • Real tim e clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year com pensation valid up to 2100 -X Z T 3d Vqqi Veat “ =
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DS1306
DS1306
20-PIN
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Untitled
Abstract: No abstract text available
Text: C h a pt er E10 Floating-Point Unit E10.1 Overview of the MB86936 Floating-Point Unit The MB86936 FPU fully conforms to the A N SI/IEEE Standard 754-1985, the SPARC Architecture Version 8 specification, and he SPARC IEEE754 Implementation Recommendation except for the Nonstandard FP (NS=1 mode implementation.
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MB86936
IEEE754
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC528257 t a r g e t s il ic o n g a t e c m o s 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION T h e T C 5 2 8 2 5 7 is a 2 M b it C M O S m u ltip o rt m e m o ry e q u ip p e d w ith a 2 6 2 ,1 4 4 -w o rd s b y ra n d o m access m e m o ry R A M p o rt an d a 5 1 2 -w o rd s b y
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TC528257
144WORDS
C-231
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