H8S/2114
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family Using the 8-Bit PWM Function Introduction This application note presents an example usage of the 8-bit PWM function of the H8S/2100 Series to implement a D/A converter. Target Device H8S/2114 H8S/2111B H8S/2140B H8S/2141B H8S/2160B
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H8S/2100
H8S/2114
H8S/2111B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
H8S/2145B
H8S/2189
H8S/2168
H8S/2114
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2005 pwm
Abstract: H8S-2110B 2110B HA-003 8c03
Text: APPLICATION NOTE H8S Family Using the 14-Bit PWM Function Introduction This application note presents an example usage of the 14-bit PWM function of the H8S/2100 Series to implement a D/A converter. Target Device H8S/2114 H8S/2110B H8S/2140B H8S/2141B H8S/2160B
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14-Bit
H8S/2100
H8S/2114
H8S/2110B
H8S/2140B
H8S/2141B
H8S/2160B
H8S/2161B
H8S/2145B
2005 pwm
H8S-2110B
2110B
HA-003
8c03
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RTAX1000S
Abstract: RTAX2000S CQFP352 RTAX-S jtag pull-up resistor 10K RTAX2000 RTAX-S library RAM EDAC SEU AC173 ACTEL
Text: Application Note AC173 Differences Between RTAX-S/SL and Axcelerator Introduction RTAX-S/SL is Actel's latest FPGA family designed for space applications and is a derivative of the Actel Axcelerator FPGA family. The RTAX-S/SL architecture is based on Actel's multi-featured, high-density AX
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AC173
RTAX1000S
RTAX2000S
CQFP352
RTAX-S
jtag pull-up resistor 10K
RTAX2000
RTAX-S library
RAM EDAC SEU
AC173
ACTEL
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FIFO4K18
Abstract: AC240 fifo vhdl fifo
Text: Application Note AC240 Using Fusion FIFO for Generating Periodic Waveforms The Actel Fusion family of Programmable System Chips PSC contains a robust collection of embedded memories including Flash memory, FlashROM, and RAM/FIFO blocks. The RAM/FIFO memory blocks include
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AC240
FIFO4K18
AC240
fifo vhdl
fifo
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APA075
Abstract: CCGA FBGA-484 datasheet APA1000 APA150 APA300 APA450 APA600 APA750 FG256
Text: Product Brief TM ProASICPLUS Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os
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32-Bit
5172161PB-16/10
APA075
CCGA
FBGA-484 datasheet
APA1000
APA150
APA300
APA450
APA600
APA750
FG256
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ADC rtl code
Abstract: AC298
Text: Application Note AC298 Multi-Channel Analog Voltage Comparator in Fusion FPGAs Introduction The Actel FusionTM Programmable System Chip PSC , the world’s first mixed-signal FPGA, integrates mixed-signal analog, Flash memory, and FPGA fabric in a monolithic PSC. Among many other analog and
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AC298
12-bit
ADC rtl code
AC298
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Untitled
Abstract: No abstract text available
Text: Application Note AC234 Designing a Web Server System Using CoreMP7 Introduction The Actel CoreMP7 processor is a soft IP version of the popular ARM7TDMI-S that has been optimized to maximize speed and minimize size in Actel Flash-based FPGAs. The combination of the ARM7TDMI-S
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AC234
Comps/Core10100
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FBGA-484
Abstract: FBGA1152 FBGA896 FBGA676 Actel PQFP208 Actel APA075 import 500k PQFP208 FBGA256 APA150 -TQ1001 datasheet
Text: Application Note AC300 ProASIC to ProASICPLUS® Design Migration Introduction The ProASICPLUS family of FPGAs with FlashLock® combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create highdensity systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family
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AC300
FBGA-484
FBGA1152
FBGA896
FBGA676
Actel PQFP208
Actel APA075
import 500k
PQFP208
FBGA256
APA150 -TQ1001 datasheet
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A42MX24
Abstract: AC297 ACTEL PQ160 CQFP 256 PIN actel A1280XL 42MX ACTEL A1240xl A32140DX PQ208 adb 230 CQ256
Text: Application Note AC297 Migrating from 1200XL and 3200DX to 42MX FPGAs Overview This application note provides the information needed for seamless migration of a design from the 1200XL and 3200DX families to the 42MX family. The Actel 42MX device architecture is based on the Actel 1200XL and 3200DX families; thus, it shares the
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AC297
1200XL
3200DX
1200XL
A42MX24
AC297
ACTEL PQ160
CQFP 256 PIN actel
A1280XL
42MX
ACTEL A1240xl
A32140DX PQ208
adb 230
CQ256
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fifo controller
Abstract: RTAX-S
Text: Application Note AC228 EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller Introduction The purpose of this application note is to specifically illustrate the following two behaviors of the FULL and EMPTY flags: • The Axcelerator and RTAX-S FIFO controller deasserts the EMPTY flag for two read clock cycles
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AC228
fifo controller
RTAX-S
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AC216
Abstract: Core8051 TRISCEND actel core 8051 80C31 ASM51 PQ208 die code actel device intel FPGA Libero
Text: Application Note AC216 Converting Triscend TE5 Designs to Actel Flash-Based FPGAs Introduction: Core8051 and the Actel Flash-Based Family of FPGAs Actel Flash-based FPGA families provide the ultimate way to implement a customizable microcontroller platform. With Core8051 Intellectual Property IP , these versatile and high-performance Flash-based
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AC216
Core8051
8051/52-compatible
programmablee8051
AC216
TRISCEND
actel core 8051
80C31
ASM51
PQ208
die code actel device
intel FPGA
Libero
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RAM512X18
Abstract: testbench verilog for 16 x 8 dualport ram FIFO4KX18 tms fifo 4bit AC237 sample vhdl code for memory write 2114 static ram 096x1
Text: Application Note AC237 Fusion SRAM/FIFO Blocks Introduction As design complexity grows, greater demands are placed upon an FPGA's embedded memory. Actel Fusion devices provide the flexibility of true dual-port as well as two-port SRAM blocks. The embedded memory,
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AC237
608-bit
RAM512X18
testbench verilog for 16 x 8 dualport ram
FIFO4KX18
tms fifo 4bit
AC237
sample vhdl code for memory write
2114 static ram
096x1
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Core1553BRM
Abstract: 1553 VHDL 1553b VHDL vhdl code for ARINC RT MIL-STD-1553B ACTEL FPGA actel core 8051 AC223 Core8051 peripherals and memory allocation of 8051 memory 2114
Text: Application Note AC223 Designing a MIL-STD-1553 System Using Core1553 and Core8051 Introduction MIL-STD-1553 is a command/response, time-multiplexed, serial data bus with a 1 Mbit/sec data rate. The bus contains a bus controller and up to 31 remote terminals. Actel Core1553 cores meet all requirements
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AC223
MIL-STD-1553
Core1553
Core8051
Core1553BRM
1553 VHDL
1553b VHDL
vhdl code for ARINC
RT MIL-STD-1553B ACTEL FPGA
actel core 8051
AC223
Core8051
peripherals and memory allocation of 8051
memory 2114
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verilog code for fir filter using DA
Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000
Text: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm
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emmc
Abstract: Core8051 Intelligent Power Module emmc schematic emmc controller emmc ip emmc write emmc firmware Specification eMMC 4.0
Text: P r o du c t B r i e f MicroTCA Power Module Reference Design Features • Complete MicroTCA Power Module Reference Design – System Management by Actel Fusion MixedSignal FPGA – Compliant to MicroTCA.0 Specification Revision 1.0 – Ready to Plug In for Evaluation and Interoperability Testing
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R5F61663N50FPV
Abstract: R5F61668RN50FPV HD64F2378RVFQ HD64F2378BVFQ R4F2117LP hd64p2128ps 3 phase dc converter afe circuit diagram igbt R5S61651CN50FPV R5F61657CN35FTV H8S/2116
Text: 2008.03 Renesas MCUs H8S Family H8SX Family www.renesas.com Learn why Renesas MCUs are preferred. Speedy + Standard + Special + Select + Safety Inheriting the world-renowned H8 architecture, and evolving it even further. This 16-bit/32-bit CISC architecture creates
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REJ01B0013-0200
R5F61663N50FPV
R5F61668RN50FPV
HD64F2378RVFQ
HD64F2378BVFQ
R4F2117LP
hd64p2128ps
3 phase dc converter afe circuit diagram igbt
R5S61651CN50FPV
R5F61657CN35FTV
H8S/2116
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M7A3P250
Abstract: QN132 A3P060 ProASIC3 A3P250 2114 SRAM A3P030 A3P125 A3P250 FG144 PQ208
Text: Product Brief ProASIC 3 Flash Family FPGAs ® ® with Optional Soft ARM Support Features and Benefits • • Advanced I/O High Capacity • • • • • • • 30 k to 1 Million System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os
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130-nm,
64-Bit
A3P030)
128-Bit
A3P030l
51700012PB-13/5
M7A3P250
QN132
A3P060
ProASIC3 A3P250
2114 SRAM
A3P030
A3P125
A3P250
FG144
PQ208
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ProASIC3
Abstract: A3PN010
Text: Advance v0.3 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process
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A3PE600
Abstract: No abstract text available
Text: v1.0 ProASIC3E Flash Family FPGAs with Optional Soft ARM® Support Features and Benefits High Capacity • 600 k to 3 Million System Gates • 108 to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os Reprogrammable Flash Technology • • • •
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64-Bit
128-Bit
A3PE600
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triggering with microprocessor
Abstract: AC272 AHB to APB
Text: Application Note AC272 CoreAI and SmartGen Implementation in Fusion Introduction The Actel FusionTM device is the world's first mixed-signal FPGA. As the ultimate Programmable System Chip PSC , Fusion integrates a configurable Analog Block (AB), Flash memory, and FPGA fabric in a
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AC272
triggering with microprocessor
AC272
AHB to APB
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car Speed Sensor
Abstract: 3 phase dc converter afe circuit diagram igbt LQFP1414-120 yokogawa 2655 LEARN ELECTRONIC ECU CAR BLOCK HD64F2639F AIRBAG EMULATION RESISTORS HD64F2378RVFQ R5F61663N50FPV 2314F
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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REJ01B0013-0200
car Speed Sensor
3 phase dc converter afe circuit diagram igbt
LQFP1414-120
yokogawa 2655
LEARN ELECTRONIC ECU CAR BLOCK
HD64F2639F
AIRBAG EMULATION RESISTORS
HD64F2378RVFQ
R5F61663N50FPV
2314F
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2114 1k x 4 SRAM
Abstract: AGLN010
Text: Advance v0.2 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS
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QN132
Abstract: 1K x4 static ram FG144 VQ100 2114 1kx4
Text: P r o du c t B r i e f IGLOOTM Low Power Flash FPGAs with Flash*FreezeTM Technology Features and Benefits Advanced I/O • • • • Low Power • • • • • • 5 µW Power Consumption in Flash*Freeze Mode 1.2 V or 1.5 V Core Voltage for Low Power
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QN132
1K x4 static ram
FG144
VQ100
2114 1kx4
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2114 1kx4
Abstract: RAM 2114 2114 SRAM 1K x4 static ram QN132
Text: P r o du c t B r i e f IGLOOTM Low Power Flash FPGAs with Flash*FreezeTM Technology Features and Benefits • • • • • • • 5 µW Power Consumption in Flash*Freeze Mode 1.2 V or 1.5 V Core Voltage for Low Power Supports Single-Voltage System Operation
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51700082PB-2/8
2114 1kx4
RAM 2114
2114 SRAM
1K x4 static ram
QN132
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