WSI PSD813F
Abstract: PSD413A1 PSD413A2 PSD813F PSD813F1
Text: Document: WSI-1018 April 27, 1998 Subject: End of Life Notification Devices: Multi-Chip Module PSD413F Devices Please discontinue use and move to OTP PSD413 Family or FLASH PSD813F Family Dear WSI Customer, Due to very limited demand, WSI is announcing the immediate obsolescence of the following MultiChip Module Devices:
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WSI-1018
PSD413F
PSD413
PSD813F
PSD413A1FH
PSD413A1FN
PSD413A2FH
PSD413A2FN
PSD413A1
PSD413A2
WSI PSD813F
PSD413A2
PSD813F1
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683XX
Abstract: 68HC11 68HC16 A15F PSD411A1 PSD411A2 psd4xx flip flop T
Text: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s
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PSD413F
PSD413
PSD411A1
PSD411A2
683XX
68HC11
68HC16
A15F
psd4xx
flip flop T
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Avance Logic
Abstract: Z80 CPU APD Arrays Avance Logic A15F PIN DIAGRAM OF 80186 683XX 68HC11 68HC16 PSD411A1 PSD411A2
Text: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s
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PSD413F
PSD413
PSD411A1
PSD411A2
Avance Logic
Z80 CPU
APD Arrays
Avance Logic A15F
PIN DIAGRAM OF 80186
683XX
68HC11
68HC16
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psd4xx
Abstract: psd3xx psd5xx
Text: PSD3xx PSD4xx PSD413F PSD5xx ZPSD3xx ZPSD4xx ZPSD5xx
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PSD413F
psd4xx
psd3xx
psd5xx
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A15F
Abstract: PSDsoft object file to hex file conversion Magic*PRO III psd4xx 80C31 PSD413A2 wsi Required Programming Algorithm Change
Text: Programmable Peripheral Application Note 047 Designing with the PSD413F – A PSD with Flash Memory By Ching Lee Introduction The PSD413F is the first member of the PSD family that supports In-System Programming ISP of the main program memory. The architecture is based on the PSD4XX core with
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PSD413F
PSD413F
0000-1FFF
h0000,
h9000,
hD555,
A15F
PSDsoft object file to hex file conversion
Magic*PRO III
psd4xx
80C31
PSD413A2
wsi Required Programming Algorithm Change
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PAC1000
Abstract: SAM448 DALLAS 2501 PSD100 WS27c010 Waferscale Integration pac1000 IR 9515 datasheet 9435, ic BA 9706 K Microcontroller AT89C51 plcc 44 pin details
Text: Reliability Summary 1999 Waferscale Integration, Inc. Reliability Summary 1999 Copyright 1999 Waferscale Integration, Inc. All rights reserved. 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-5916 Web Site: http://www.waferscale.com
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8/10/99mc
PAC1000
SAM448
DALLAS 2501
PSD100
WS27c010
Waferscale Integration pac1000
IR 9515 datasheet
9435, ic
BA 9706 K
Microcontroller AT89C51 plcc 44 pin details
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SAM448
Abstract: pac1000 PSD100 PAC1000A BA 9515 ba 4913 WS*57c257 ws57c257 ws57c43 psi c 275 9 121
Text: Reliability Summary 1997 Copyright 1997 WaferScale Integration, Inc. All rights reserved. 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Facsimile: 510-657-5916 Web Site: http://www.wsipsd.com Printed in U. S. A. Return to Main Menu Table of Contents
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WS59032
2-201-1A
91-1624-AC
CA112
101-Pin
92-201-1B
SAM448
pac1000
PSD100
PAC1000A
BA 9515
ba 4913
WS*57c257
ws57c257
ws57c43
psi c 275 9 121
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Untitled
Abstract: No abstract text available
Text: PSD413F Family PSD413F Pin Assignments Pin Ho. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 68-Pin PLDCC Package GND ADIO_7 ADIO_6 ADIO_5 ADIO_4 ADIO_3 ADIO_2 ADIO_1 ADIO_0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO v cc
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PSD413F
68-Pin
ADICL15
ADICL12
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Untitled
Abstract: No abstract text available
Text: PSD413F Family General Description The PSD4XX series of Field Programmable Microcontroller Peripherals represent a major advance in the evolution of Programmable Peripherals. They combine an innovative architecture with state of the art technology to provide user PROGRAMMABILITY
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PSD413F
PSD413A2F.
PSD413F
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Untitled
Abstract: No abstract text available
Text: PSD413F Family System Configuration The CSIOP signal, which is generated by the DPLD, selects the internal I/O devices or registers. The CSIOP signal takes up 256 bytes of address space and is defined by the user in the PSDSoft Software. The following is an address offset map for the various
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PSD413F
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D413a
Abstract: No abstract text available
Text: PSB413F Family Table 2. PSD413F Pin Descriptions The following table describes the pin names and pin functions of the PSD413F. Pins that have multiple names and/or functions are defined by user configuration. Pin Name ADIOO - ADI015 Pin Function Address/data bus
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PSB413F
PSD413F
PSD413F.
ADI015
D413a
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d413a
Abstract: No abstract text available
Text: PSD413F Family I/O Ports There are 5 program m able 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These ports all have m ultiple operating m odes, depending on th e configuration. Som e of the basic functions are providing input/output fo r the ZPLD, or can be used for standard I/O. Each
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PSD413F
d413a
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Untitled
Abstract: No abstract text available
Text: PSD413F Family Figure 33. Read Timing tAVLX _ tLXAX \ / - ALE/AS tLVLX A/D MULTIPLEXED BUS ADDRESS VALID DATA VALID tAVQV ADDRESS NON-MULTIPLEXED BUS \ r yz ADDRESS VALID DATA NON-MULTIPLEXED BUS & DATA VALID tSLQV tRLQV IRHQX «RLRH _RD PSEN, DS
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PSD413F
Topical12
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T flip flop pin configuration
Abstract: No abstract text available
Text: PSD413F Family The PSD413A2F ZPLD Block Key Features □ 2 Embedded ZPLD devices □ 24 macrocells □ Combinatorial/registered outputs □ Maximum 126 product terms □ Programmable output polarity □ User configured register clear/preset □ User configured register clock input
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PSD413F
PSD413A2F
T flip flop pin configuration
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Untitled
Abstract: No abstract text available
Text: PSD413F Family AC/DC The following tables describe the AD/DC parameters of the PSD413F family: PSIiMNitBfS □ DC Electrical Specification □ AC Timing Specification • ZPLD Timing - Combinatorial Delays - Synchronous Clock Mode - Asynchronous Clock Mode
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PSD413F
PSB413F
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Untitled
Abstract: No abstract text available
Text: PSD413F Family Power Management Unit The PSD413F provides many power saving options. By configuring the PMMRs Power Management Mode Registers , the user can reduce power consumption. Table 15 shows the bit configuration of the PMMRO and PMMR1. The microcontroller is able to
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PSD413F
PSD413F:
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Untitled
Abstract: No abstract text available
Text: PSD413F Family Figure 44. Drawing J5 68-Pin Plastic Leaded Chip Carrier PLDCC (Package TypeJ) o 1- M n « 2 2 2 2 2 2 2 2 û 2 2 2 2 2 2 2 2 S O< Q< <Û <O <Q <p <a ZC Û< O< Q< O< D O G O < < < < Figure 45. Drawing J5 68-Pin Plastic Leaded Chip Carrier
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PSD413F
68-Pin
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80196 MEMORY INTERFACE
Abstract: 80196 programs 80196 internal architecture diagram
Text: Programmable Peripheral PSD413F Family Advance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI's
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PSD413F
PSD413
PSD411A1
PSD411A2
80196 MEMORY INTERFACE
80196 programs
80196 internal architecture diagram
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Untitled
Abstract: No abstract text available
Text: PSD413F Family The PSD413F Architecture The PSD413F consists of five major functional blocks: □ zpld Block □ Bus Interface □ I/O Ports □ Memory Block □ Power Management Unit The functions of each block are described in the following sections. Many of the blocks
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PSD413F
PSD413A1F
PSD413A2F
PS0413A1F
PSB413A1F
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Untitled
Abstract: No abstract text available
Text: PSD413F Family Memory Block The PSD413F is a multi-chip module that includes a PSD4XX die and a 1 megabit Flash memory die. The PSD4XX includes 8 Kbytes of O T P Boot EPROM; the Flash die provides 128 Kbytes of Flash memory. The O T P Boot E P R O M is used for system boot up and for
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PSD413F
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wsi Required Programming Algorithm Change
Abstract: No abstract text available
Text: Appendix A The Operation and Programming Algorithm Used In the PSD413F Flash Memory Abstract This Appendix describes the operation and programming algorithm used in the Flash memory inside the PSD413F. Portions of this document are copyrighted by AMD. General
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PSD413F
PSD413F.
wsi Required Programming Algorithm Change
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Untitled
Abstract: No abstract text available
Text: PSD413F Family Page Register The Page Register is 4 bits wide and consists of four D flip flops.The outputs of the Register PGRO - PGR3 are connected to the input bus of the ZPLD. By including the four outputs as inputs to the DPLD, the addressing capability of the microcontroller is increased by a
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PSD413F
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MICROCONTROLLER 8031
Abstract: No abstract text available
Text: PSB413F Family Bus Interface The Bus Interface is very flexible and can be configured to interface to most microcontrollers with no glue logic. Table 7 lists some of the bus types to which the Bus Interface is able to interface. Table 7. Typical Microcontroller Bus types
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PSB413F
68HC11
PSD413FH
PSD413F
68HC11
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
MICROCONTROLLER 8031
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