AOI222
Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:
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5962-01B01
4138E
AOI222
AOI2223
AOI222H
MH1099
MH1242
0.35-um CMOS standard cell library inverter
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tristate buffer
Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E
Text: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to
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4110F
tristate buffer
smd transistor AO
HEX TO DECIMAL
tristate buffer cmos
A101
A201
MH1099E
MH1156E
PO11F
MH1332E
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PO88
Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Text: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:
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250MHz
220MHz
800MHz
5962-01B01
PO88
ttl buffer
AOI222
AOI2223
AOI2223H
AOI222H
MH1099
MH1242
PRD21
PRD29V5
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TEMIC PLD
Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The
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Transistor Equivalent list po55
Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos
Text: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to
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