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    PPECL2 Price and Stock

    ABB Low Voltage Products and Systems PPECL2024

    Girder Clip, Single Cable, 24Mm; Clip Type:Girder Clip; Clip Diameter:24Mm; Mounting Hole Dia:-; Product Range:E-Klips, Ecl Series; Svhc:No Svhc (12-Jan-2017); Body Plating:Zinc; Cable Diameter Max:24Mm; Cable Diameter Min:19Mm; Rohs Compliant: Na |Abb PPECL2024 (Alternate Part Number: 5414363085607
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Newark PPECL2024 Pack 3 1
    • 1 $48.89
    • 10 $43.06
    • 100 $36.07
    • 1000 $36.07
    • 10000 $36.07
    		Buy Now

    Rhombus Industries Inc PPECL2-2

    ACTIVE DELAY LINE, PROGRAMMABLE, 1-FUNC, 15-TAP, ECL
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components PPECL2-2 77
    • 1 $7.5
    • 10 $3.75
    • 100 $3.25
    • 1000 $3.25
    • 10000 $3.25
    		Buy Now

    Rhombus Industries Inc PPECL2-4

    ACTIVE DELAY LINE, PROGRAMMABLE, 1-FUNC, 15-TAP, ECL
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components PPECL2-4 1
    • 1 $7.5
    • 10 $5
    • 100 $5
    • 1000 $5
    • 10000 $5
    		Buy Now

    PPECL2 Datasheets (11)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    PPECL2-1 Rhombus Industries Delay Line PROG 1IN 1NS ABS 15NS MAX Original PDF
    PPECL2-1.25 Rhombus Industries Delay Line PROG 1IN 1.25NS ABS 18.75NS MAX Original PDF
    PPECL2-1.5 Rhombus Industries Delay Line PROG 1IN 1.5NS ABS 22.5NS MAX Original PDF
    PPECL2-2 Rhombus Industries Delay Line PROG 1IN 2NS ABS 30NS MAX Original PDF
    PPECL2-2.5 Rhombus Industries Delay Line PROG 1IN 2.5NS ABS 37.5NS MAX Original PDF
    PPECL2-3 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF
    PPECL2-4 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF
    PPECL2-5 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF
    PPECL2P25 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF
    PPECL2P50 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF
    PPECL2P75 Rhombus Industries 100K ECL Logic 4-Bit Programmable Delay Module Original PDF

    PPECL2 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    APA600

    Abstract: AA23 APA075 APA1000 APA150 APA300 APA450 APA750
    Text: ProASICPLUS Flash Family FPGAs Package Pin Assignments 100-Pin TQFP 1 100 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at . v5.8 2-1 ProASICPLUS Flash Family FPGAs


    Original     		100-Pin APA075 APA150 APA600 AA23 APA075 APA1000 APA150 APA300 APA450 APA750 PDF

    eclpw

    Abstract: pulse width generator
    Text: 10K / 10KH ECL Logic Pulse Width Control Modules Electrical Specifications at 25OC Electrical Specifications at 25OC 10KH ECL Pulse Width Generator Modules 10K ECL Pulse Width Generator Modules Maximum Freq. MHz 77.0 67.0 59.0 53.0 48.0 43.0 31.0 23.0 19.0


    Original     		ECLPWG-10 ECLPWG-15 ECLPWG-20 ECLPWG-25 ECLPWG-30 ECLPWG-40 ECLPWG-50 ECLPWG-60 ECLPWG-75 ECLPWG-100 eclpw pulse width generator PDF

    PPECL2

    Abstract: 15801 PPECL2P25 PPECL2P50 PPECL2P75
    Text: 100K ECL Logic 4-Bit Programmable Delay Modules Schematic Diagram ELECTRICAL SPECIFICATIONS @ 25°C Inherent Delay Time Step 0 . 2.00 ns + 0.50 ns Delay Per Programming Step . See Table Maximum Programming Delay . 2 ns + (15 x Step)


    Original     		24-Pin PPECL2 15801 PPECL2P25 PPECL2P50 PPECL2P75 PDF

    Untitled

    Abstract: No abstract text available
    Text: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		PDF

    schematic diagram online UPS for high frequency

    Abstract: ag19
    Text: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process


    Original     		PDF

    APA750

    Abstract: GL25 4kx8 sram
    Text: v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process


    Original     		PDF

    APA1000

    Abstract: actel PLL schematic AD 149 AE9 APA075 APA150 APA300 APA450 APA750 624 CCGA ACTEL proASIC PLUS APA450
    Text: v5.5 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Advanced v1.2 ProASICPLUS Military and Aerospace FPGAs Fe a t ur es an d B e ne f i ts High C apaci t y • 300,000 to 1 million System Gates • 72k to 198kbits of Two-Port SRAM • 158 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy • Operates over Full Military Temperature Range –55°C to


    Original     		198kbits PDF

    gl324

    Abstract: 180 nm CMOS standard cell library AMI 198kB ProASICPLUS Flash Family FPGAs v3.2 APA075
    Text: v3.2 TM ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y


    Original     		198kbits gl324 180 nm CMOS standard cell library AMI 198kB ProASICPLUS Flash Family FPGAs v3.2 APA075 PDF

    Untitled

    Abstract: No abstract text available
    Text: v5.4 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		32-Bit PDF

    JC 201 SC

    Abstract: GL324 ProASICPLUS Flash Family FPGAs v3.1
    Text: v3.1 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy


    Original     		198kbits JC 201 SC GL324 ProASICPLUS Flash Family FPGAs v3.1 PDF

    schematic diagram UPS ica

    Abstract: TBD 234 V12 schematic diagram UPS 600 Power tree CQFP CQFP352 ProASICPLUS Flash Family FPGAs v3.0
    Text: Advanced v1.2 ProASICPLUS Military and Aerospace FPGAs Fe a t ur es an d B e ne f i ts High C apaci t y • 300,000 to 1 million System Gates • 72k to 198kbits of Two-Port SRAM • 158 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy • Operates over Full Military Temperature Range –55°C to


    Original     		198kbits schematic diagram UPS ica TBD 234 V12 schematic diagram UPS 600 Power tree CQFP CQFP352 ProASICPLUS Flash Family FPGAs v3.0 PDF

    GL324

    Abstract: ads pa-600 ups 400 ec
    Text: v3.3 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy


    Original     		198kbits GL324 ads pa-600 ups 400 ec PDF

    G1152

    Abstract: RAM256X9SST
    Text: v5.2 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		32-Bit G1152 RAM256X9SST PDF

    APA600-PQ208

    Abstract: APA075 APA1000 APA150 APA300 APA450 APA750 APA600-PQ208M T10IO
    Text: v5.9 ProASICPLUS® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 K to 198 Kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		32-Bit APA600-PQ208 APA075 APA1000 APA150 APA300 APA450 APA750 APA600-PQ208M T10IO PDF

    philips cx50

    Abstract: at24lc02 FRC 40 PIN Male connector 88E1145 FRC 14 PIN Male connector hynix mcp marvell 88e1145 schematic atx 2.03 P4 capacitor 0.1uf 400v Indutor
    Text: MPC8555E Configurable Development System Reference Manual Supports MPC8555E MPC8541E MPC8555CDSx3RM Rev. 1, 11/2006 Contents Paragraph Number Title Page Number Contents About This Book Audience . xiii


    Original     		MPC8555E MPC8541E MPC8555CDSx3RM philips cx50 at24lc02 FRC 40 PIN Male connector 88E1145 FRC 14 PIN Male connector hynix mcp marvell 88e1145 schematic atx 2.03 P4 capacitor 0.1uf 400v Indutor PDF

    ACTEL CCGA 624 mechanical

    Abstract: APA075
    Text: v4.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates


    Original     		PDF

    JESD 85

    Abstract: 130 nm CMOS standard cell library ST GL25 Core from Libero schematic diagram UPS ica
    Text: Advanced v1.1 ProASICPLUS Military and Aerospace FPGAs Fe a t ur es an d B e ne f i ts High C apaci t y • 300,000 to 1 million System Gates • 72k to 198kbits of Two-Port SRAM • 158 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy • Operates over Full Military Temperature Range –55°C to


    Original     		198kbits JESD 85 130 nm CMOS standard cell library ST GL25 Core from Libero schematic diagram UPS ica PDF

    ProASIC PLUS v0.1

    Abstract: No abstract text available
    Text: v3.5 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-Based CMOS Process


    Original     		PDF

    schematic diagram ups 600 actel silicon sculptor

    Abstract: FLASHPRO LITE GL324 ProASICPLUS Flash Family FPGAs v3.0 W5108 GL25 APA075 APA150 APA300 APA600
    Text: v3.0 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy


    Original     		198kbits schematic diagram ups 600 actel silicon sculptor FLASHPRO LITE GL324 ProASICPLUS Flash Family FPGAs v3.0 W5108 GL25 APA075 APA150 APA300 APA600 PDF

    20STEP

    Abstract: No abstract text available
    Text: RHOMBUS I N D U S T R I E S 27E » IN C 7724120 0000141 • 1 ■ 10K & 100K ECL BUFFERED DELAY MODULES 3-BIT 10K ECL PROGRAMMABLE THROUGH-HOLE DIL. PECL3-XX SERIES PART NUMBER PECL3-.5 PECL3-1 PECL3-2 PECL3-3 PECL3-4 PECL3-5 PECL3-6


    OCR Scan     		PECL3-10 20STEP PDF

    Untitled

    Abstract: No abstract text available
    Text: RHOMBUS IN D U S T R IE S INC 45E » IRHB 7 7 B IH 2 0 0000253 1 10K & 100K ECL BUFFERED DELAY MODULES r-V7-/7 3-BIT 10K ECL PROGRAMMABLE THROUGH -HOLE D IL STEP Mn. Max. Max. ns (IW) D«v. (m DELAY (ns) PART NUMBER PECL3-0.5 PECL3-1 PECL3-2 P EC LM PECL3-4


    OCR Scan     		PECL3-10 PDF

    Untitled

    Abstract: No abstract text available
    Text: RHO H BU S I N D U S T R I E S INC b3E D 7 7 2 14ciED 0D 0DM 34 ETt. RHB 8 Tap 100K ECL Buffered Delay Modules IN Vcc 24] Vee Vcc [Til H fl3l G ENERAL: For Operating Specifications and Test Conditions, see Tables VI and VIII on page 7 of this catalog. Delays specified for the Leading Edge.


    OCR Scan     		300ppm/Â DOECL-6/93 PDF

    Untitled

    Abstract: No abstract text available
    Text: 1 0 K /1 0 K H ECL Logic Pulse Width Control Modules Electrical Specifications at 25°C Part Number ECLPWG-5 ECLPWG-6 ECLPWG-7 ECLPWG-8 ECLPWG-9 ECLPWG-10 ECLPWG-15 ECLPWG-20 ECLPWG-25 ECLPWG-30 ECLPWG-40 ECLPWG-50 ECLPWG-60 ECLPWG-75 ECLPWG-100 • Triggered by the input's rising edge input pulse


    OCR Scan     		ECLPWG-10 ECLPWG-15 ECLPWG-20 ECLPWG-25 ECLPWG-30 ECLPWG-40 ECLPWG-50 ECLPWG-60 ECLPWG-75 ECLPWG-100 PDF