XTAL1
Abstract: pca816 addr alu circuit with transistor 0p07
Text: P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM PORT 2 LATCH FLASH 8 B REGISTER STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs TIMERS PSW PC INCREMENTER P.C.A. 8 16 PSEN ALE EAVPP TIMING
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Hitachi PIX-8144
Abstract: Hitachi PIX 8144 Pix-8144 PIX 8144 hitachi 8144 CY7C025-AC dual port 16 SRAM PLCC CY7C024 CY7C0241 CY7C0251
Text: Qualification Report QTP 96091/96393, Version 2.0 September 1996 Dual Port SRAM - R28 Technology, 6% Shrink CY7C0251 8K x 18 Dual Port SRAM CY7C025 8K x 16 Dual Port SRAM CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM
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CY7C0251
CY7C025
CY7C0241
CY7C024
CY7C145
CY7C144
CY7C139
CY7C138
CY7C133
CY7C143
Hitachi PIX-8144
Hitachi PIX 8144
Pix-8144
PIX 8144
hitachi 8144
CY7C025-AC
dual port 16 SRAM PLCC
CY7C024
CY7C0241
CY7C0251
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96182
Abstract: cy7c024 CY131 CY7C0241 CY7C133 CY7C1342 CY7C135 CY7C138 CY7C139 CY7C143
Text: Qualification Report September 1996, QTP# 96182/96354, Version 2.0 Dual Port SRAM - R28 Technology CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM CY7C144 8K x 8 Dual Port SRAM CY7C139 4K x 9 Dual Port SRAM CY7C134
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CY7C0241
CY7C024
CY7C145
CY7C144
CY7C139
CY7C134
CY7C1342
CY7C135
CY7C138
CY7C133
96182
cy7c024
CY131
CY7C0241
CY7C133
CY7C1342
CY7C135
CY7C138
CY7C139
CY7C143
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ADI1290
Abstract: DSP56001 MBD301 MC6800 MC68000
Text: SECTION 9 PORT A Port A is the memory expansion port that can be used for either memory expansion or for memory-mapped I/O see 2.9.1 Expansion Port (Port A . A number of features make port A versatile and easy to use. These features provide a low-parts-count connection
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16-bit
64K-word
24-bit
DSP56000/DSP56001
DSP56000
DSP56000/
DSP56001
ADI1290
DSP56001
MBD301
MC6800
MC68000
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dual port SRAM PLCC
Abstract: CY7C133 CY7C138 CY7C139 CY7C143 CY7C144 CY7C145 CY7C016 CY7C024 CY7C0241
Text: Qualification Report May 1996, QTP# 95226, Version 1.0 Dual Port SRAM - R28 Technology Thin Quad Flat Pack Package CY7C0251 8K x 18 Dual Port SRAM CY7C025 8K x 16 Dual Port SRAM CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM
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CY7C0251
CY7C025
CY7C0241
CY7C024
CY7C145
CY7C144
CY7C139
CY7C138
CY7C133
CY7C143
dual port SRAM PLCC
CY7C133
CY7C138
CY7C139
CY7C143
CY7C144
CY7C145
CY7C016
CY7C024
CY7C0241
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Ablestik
Abstract: CY7C024 CY7C0241 CY7C139 CY7C144 CY7C145
Text: Cypress Semiconductor Qualification Report QTP# 98393 VERSION 1.3 March, 1999 Dual Port SRAM - R28 Technology - Fab 2 CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM CY7C144 8K x 8 Dual Port SRAM CY7C139 4K x 9 Dual Port SRAM
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CY7C0241
CY7C024
CY7C145
CY7C144
CY7C139
CY7C1342/135/138
CY7C133/143
7C0241C)
CY7C0251-AC
Ablestik
CY7C024
CY7C0241
CY7C139
CY7C144
CY7C145
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AL010
Abstract: AR11 AR12 CY7C132 CY7C142 DR31 "Single-Port RAM"
Text: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in
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Comm1997.
AL010
AR11
AR12
CY7C132
CY7C142
DR31
"Single-Port RAM"
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dual port ram
Abstract: AR11 AR12 CY7C132 CY7C142 DR31
Text: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in
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AD3b
Abstract: ad4a AD7B dual-port RAM DS1609 DS1609S AD5A 256 byte dual port memory
Text: DS1609 DS1609 Dual Port RAM FEATURES PIN ASSIGNMENT • Totally asynchronous 256 byte dual port memory PORT A PORT B AD7A 1 24 VCC AD6A 2 23 OEB AD5A 3 22 CEB port memory cell allows random access with minimum arbitration AD4A 4 21 WEB AD3A 5 20 AD0B • Each port has standard independent RAM control sig-
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DS1609
AD3b
ad4a
AD7B
dual-port RAM
DS1609
DS1609S
AD5A
256 byte dual port memory
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ADI1290
Abstract: rom 2716 DSP56001 users manual DSP56001 MBD301 MC6800 MC68000
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SECTION 9 PORT A Port A is the memory expansion port that can be used for either memory expansion or for memory-mapped I/O see 2.9.1 Expansion Port (Port A . A number of features make port A versatile and easy to use. These features provide a low-parts-count connection
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16-bit
64K-word
24-bit
DSP56000/DSP56001
ADI1290
rom 2716
DSP56001 users manual
DSP56001
MBD301
MC6800
MC68000
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Dp 140c
Abstract: CY7C006 CY7C016 CY7C025 CY7C0251 JESD22 8361H
Text: Cypress Semiconductor Qualification Report QTP# 98302 VERSION 1.2 March, 1999 Dual Port SRAM - R28 Technology - Fab 2 CY7C025 8K x 16 Dual Port SRAM CY7C0251 8K x 18 Dual Port SRAM CY7C006 16K x 8 Dual Port SRAM CY7C016 16K x 9 Dual Port SRAM Cypress Semiconductor
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CY7C025
CY7C0251
CY7C006
CY7C016
7C0251D)
7C0251D
CY7C0251-AC
Dp 140c
CY7C006
CY7C016
CY7C025
CY7C0251
JESD22
8361H
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transistor p35
Abstract: UM97Z8X0104 P2M TRANSISTOR AD08 transistor P32 25
Text: USER’S MANUAL 5 CHAPTER 5 I/O PORTS 5.1 I/O PORTS The Z8 has up to 32 lines dedicated to input and output. These lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and Port 3. Port 0 is nibble programmable as input, output, or address. Port 1 is byte configurable as
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16/1M
UM97Z8X0104
transistor p35
UM97Z8X0104
P2M TRANSISTOR
AD08
transistor P32 25
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BC634
Abstract: AA012 DSP56800 bc645 BC699 bc657
Text: SECTION 12 JTAG PORT DSP56L811 User’s Manual 12-1 JTAG Port 12.1 12.2 12.3 12.4 12.5 12-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 JTAG PORT ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 12-4 JTAG/ONCE PORT PINOUT. . . . . . . . . . . . . . . . . . . . . . . . 12-5
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DSP56L811
BC634
AA012
DSP56800
bc645
BC699
bc657
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CYPRESS CROSS REFERENCE dual port sram
Abstract: 1024 byte dual port memory "8-Bit Microprocessors" CY7C132 dual port sram dual port SRAM PLCC dual-port RAM AR11 AR12 CY7C142
Text: fax id: 5300 Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in
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CYD18S18V18-200BBAXI
Abstract: FullFlex36 CYD36S18V18-167BGXI
Text: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR operation on each port
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FullFlex72
72-bit
CYD18S18V18-200BBAXI
FullFlex36
CYD36S18V18-167BGXI
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ECP88
Abstract: No abstract text available
Text: PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi directional parallel port SPP , the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the
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FDC37C669
ECP88
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intel 82360SL
Abstract: 82360SL B2091
Text: intel« 82091AA 6.0 PARALLEL PORT The 82091AA parallel port can be configured for four parallel port modes. These parallel port modes and the associated parallel interface protocols are: Parallel Port Mode Parallel Interface Protocol ISA-Compatible Mode Compatibility, Nibble
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82091AA
82091AA
intel 82360SL
82360SL
B2091
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TM P90C840A/841 A 3.5.4 Port 3 P30~P37 Port 3 is an 8-bit general-purpose I/O port P3 with fixed I/O function. All bits of the output latch are initialized to “1” by resetting, and “High level” is generated to the output port. In addition to the I/O port function, P30~P34 have the I/O function for the internal
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P90C840A/841
MCU90-41
TMP90C840A/841A
MCU90-42
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Untitled
Abstract: No abstract text available
Text: FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY Integrated Device Technology, Inc* FEATURES PRELIMINARY IDT73210/A/B IDT73211/A/B 73210/211 Single-level pipeline register from Port A to Port B 73210 Two level pipeline register from Port B to Port A 73211 Single level pipeline register from Port B to Port A
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IDT73210/A/B
IDT73211/A/B
IL-STD-883,
32-pin
IDT73210
MASS771
IDT73210/A/B,
IDT73211/A/B
MIL-STD-883,
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D42264
Abstract: HPD42264C-10 JHPD42264 JJPD42264 JUPD42264 PPD42264 D4226
Text: NEC JVPD42264 Dual-Port Graphics Buffer N EC E lec tro n ics Inc. Description Features The ¿iPD42264 is a dual-port graphics buffer equipped with a 64K x 4-bit random access port and a 256 x 4-bit serial read port. The serial read port is connected to an
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uPD42264
1024-bit
JJPD42264
-6609B
D42264
HPD42264C-10
JHPD42264
JJPD42264
JUPD42264
PPD42264
D4226
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TMP90C840A/841A 3.5.5 P o rt4 P 40~ P 4 3 Port 4 is a 4-bit port P4 intended only for the output. All bits of the output latch are initialized to “0” by resetting, and “0” is generated to the port. In addition to the output port function, it works as an address bus (A16~A19). The
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TMP90C840A/841A
CU90-42
MCU90-43
D02TDGD
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hpc46900
Abstract: uPI Semiconductor package h8c
Text: PRELIM INARY HPC16900/HPC26900/HPC36900/HPC46900 PEARL Port Expander And Re-creation Logic G eneral Description The PEARL is a peripheral device which re-creates Port A and four bits of Port B when used with HPC family microcon trollers. An additional 16-bit port Port PC is configured as
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HPC16900/HPC26900/HPC36900/HPC46900
HPC16900/HPC26900/HPC36900/HPC46900
16-bit
HPC16900V
hpc46900
uPI Semiconductor
package h8c
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Untitled
Abstract: No abstract text available
Text: VLSI Technology , in c . ADVANCE INFORMATION BUSY FLAGS VT71321 • VT71421 _ LOW until the right port reads data from the same location. Similarly, if the right port writes to memory location 7FE HEX , the left port Interrupt flag (INTL) is latched LOW
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VT71321
VT71421
Si995x
O-252
Si995x,
9951DY
9956DY
9950DY
9954DY
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upd42274
Abstract: PD42274-80 JPD42274 PD4227
Text: NEC pPD42274-80 Dual-Port Graphics Buffer NEC Electronics Inc. Description Features The pPD42274-80 is a dual-port graphics buffer equipped with a 256Kx 4-bit random access port and a 512 x 4-bit serial read port. The serial read port is connected to an internal 2048-bit data register through
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uPD42274-80
256Kx
2048-bit
/UPD42274-80
jnPD42274-80
/JPD42274-80
1PD42274-80
ffPD42274-80
JJPD42274-80
upd42274
PD42274-80
JPD42274
PD4227
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