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    CY7C139 Price and Stock

    Infineon Technologies AG CY7C1399BN-12VXIT

    IC SRAM 256KBIT PARALLEL 28SOJ
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    Infineon Technologies AG CY7C1399BN-12VXI

    IC SRAM 256KBIT PARALLEL 28SOJ
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    DigiKey CY7C1399BN-12VXI Tube 523 1
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    Rochester Electronics LLC CY7C1399-15VC

    IC SRAM 256KBIT PARALLEL 28SOJ
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    DigiKey CY7C1399-15VC Bulk 201
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    Infineon Technologies AG CY7C1399BN-12ZXCT

    IC SRAM 256KBIT PAR 28TSOP I
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    Rochester Electronics LLC CY7C1399BN-15VXCT

    IC SRAM 256KBIT PARALLEL 28SOJ
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    DigiKey CY7C1399BN-15VXCT Bulk 452
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    Find more CY7C139 price and stock on Findchips.com

    CY7C139 Datasheets (270)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C139 Cypress Semiconductor Memory : Dual-Ports Original PDF
    CY7C139 Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-15 Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-15JC Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-15JC Cypress Semiconductor Memory : Dual-Ports Original PDF
    CY7C139-15JC Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Scan PDF
    CY7C139-25 Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-25JC Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-25JC Cypress Semiconductor Memory : Dual-Ports Original PDF
    CY7C139-25JC Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Scan PDF
    CY7C139-25JI Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-25JI Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Original PDF
    CY7C139-25JI Cypress Semiconductor 4K x 8/9 Dual-Port Static RAM Scan PDF
    CY7C139-25JXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36KBIT 25NS 68PLCC Original PDF
    CY7C1392AV18 Cypress Semiconductor 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Original PDF
    CY7C1392AV18-167BZC Cypress Semiconductor 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Original PDF
    CY7C1392AV18-200BZC Cypress Semiconductor Original PDF
    CY7C1392AV18-250BZC Cypress Semiconductor Original PDF
    CY7C1392BV18 Cypress Semiconductor 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Original PDF
    CY7C1392BV18-167BZXC Cypress Semiconductor 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Original PDF
    ...

    CY7C139 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    016v

    Abstract: No abstract text available
    Text: fax id: 5212 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device


    Original     		CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V 4K/8K/16K 80-pin 7C145V, 7C007V, 7C016V 7C017V) 64-pin 7C006V 016v PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz PDF

    9l reset

    Abstract: No abstract text available
    Text: 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • On-chip arbitration logic


    Original     		CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V 4K/8K/16K/32K 80-pin 7C145V, 7C007V, 7C016V 7C017V) 64-pin 7C006V 9l reset PDF

    1709 013

    Abstract: CY7C1399BN CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC
    Text: CY7C1399BN 256K 32K x 8 Static RAM Features expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.


    Original     		CY7C1399BN CY7C1399BN 1709 013 CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC PDF

    Untitled

    Abstract: No abstract text available
    Text: 399 CY7C1399 32K x 8 3.3V Static RAM Features • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 255 mW max. • Low CMOS standby power (L) — 180 µW (max.), f=fMAX • 2.0V data retention (L)


    Original     		CY7C1399 CY7C1399 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces


    Original     		CY7C1393BV18 CY7C1394BV18 CY7C1393BV18, CY7C1394BV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency


    Original     		CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: 399B CY7C1399B 32K x 8 3.3V Static RAM Features pansion is provided by an active LOW Chip Enable CE and active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.


    Original     		CY7C1399B CY7C1399B PDF

    CYPRESS CROSS REFERENCE dual port sram

    Abstract: CY7C006AV CY7C007AV CY7C016AV CY7C017AV CY7C138AV CY7C139AV CY7C144AV CY7C145AV
    Text: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous


    Original     		CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV CY7C144AV CY7C006AV CYPRESS CROSS REFERENCE dual port sram PDF

    SEM 2005 16 PINS

    Abstract: pin diagram of sem 2005 CY7C138 CY7C139 sem 2005 16 pin 25j81
    Text: CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization CY7C138


    Original     		CY7C138 CY7C1394K CY7C138 CY7C139 CY7C138) CY7C139) 65-micron CY7C138/CY7C139 SEM 2005 16 PINS pin diagram of sem 2005 CY7C139 sem 2005 16 pin 25j81 PDF

    Untitled

    Abstract: No abstract text available
    Text: 1 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV PRELIMINARY 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations CY7C0138AV/144AV/


    Original     		CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 4K/8K/16K/32K CY7C0138AV/144AV/ 006AV/007AV) CY7C0139AV/145AV/ 016AV/017AV) PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1399BN 256 K 32 K x 8 Static RAM Functional Description Features The CY7C1399BN is a high-performance 3.3 V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tristate drivers. The


    Original     		CY7C1399BN CY7C1399BN PDF

    CY7C1399B

    Abstract: CY7C1399B-12VC CY7C1399B-15VXC
    Text: CY7C1399B 256K 32K x 8 Static RAM Features active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. • Single 3.3V power supply • Ideal for low-voltage cache memory applications


    Original     		CY7C1399B CY7C1399B CY7C1399B-12VC CY7C1399B-15VXC PDF

    577w

    Abstract: CY7C1399V A6213
    Text: CY7C1399V 32K x 8 3.0V Static RAM Features D D Single 3.0V The CY7C1399V is a highĆperformance 3.0V CMOS static RAM organized as 32,768 words by 8 bits. Easy memory exĆ pansion is provided by an active LOW chip enable CE and active LOW output enĆ able (OE) and threeĆstate drivers. The deĆ


    Original     		CY7C1399V CY7C1399V 577w A6213 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit Density 1M x 18, 512K x 36 ■ 300 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces


    Original     		CY7C1393CV18 CY7C1394CV18 18-Mbit PDF

    CY7C1399

    Abstract: EME-6300H
    Text: Qualification Report July 1996, QTP# 95417, Version 2.0 CY7C1399 32K x 8, 3.3V Static RAM PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:


    Original     		CY7C1399 28-Lead 28-Lead, 300-Mil 7C1399C CY7C1399-VC CY7C1399 EME-6300H PDF

    CY7C1395V25

    Abstract: No abstract text available
    Text: 395 CY7C1395 CY7C1395V25 PRELIMINARY 2M x36 PBSRAM with NoBL -Burst Architecture Features to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1395V25 operates with a 2.5V power supply and the CY7C1395 operates


    Original     		CY7C1395 CY7C1395V25 CY7C1395V25 CY7C1395 CY7C1395/CY7C1395V25 PDF

    70V06

    Abstract: IDT70V05
    Text: 1 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device


    Original     		CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V 4K/8K/16K/32K 68-pin 64-pin 7C006V 7C144V) IDT70V05, 70V06, 70V07. 70V06 IDT70V05 PDF

    CY7C1392V18

    Abstract: CY7C1393V18 CY7C1394V18
    Text: 392V18 CY7C1392V18 CY7C1393V18 CY7C1394V18 ADVANCE INFORMATION 18-Mb SRAM with DDR-II SIO Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth


    Original     		392V18 CY7C1392V18 CY7C1393V18 CY7C1394V18 18-Mb 300-MHz CY7C1392V18 CY7C1393V18 CY7C1394V18 PDF

    68LEAD

    Abstract: No abstract text available
    Text: CY7C138, CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • True Dual-Ported memory cells that enable simultaneous reads of the same memory location ■ 4K x 8 organization CY7C138 ■ 4K x 9 organization (CY7C139)


    Original     		CY7C138, CY7C139 CY7C138 CY7C139 CY7C138/9 16/18-bit 68LEAD PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit PDF

    CY7C1399BN

    Abstract: CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC
    Text: CY7C1399BN 256K 32K x 8 Static RAM Features expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.


    Original     		CY7C1399BN CY7C1399BN CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces


    Original     		CY7C1393BV18 CY7C1394BV18 CY7C1393BV18, CY7C1394BV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: 7c1399: Monday, November 16,1992 Revision: Wednesday, January 6,1993 CY7C1399 ADVANCED INFORMATION CYPRESS t SEMICONDUCTOR = ' 3.3V 32Kx 8 Static RAM • Automatic power-down when deselected Features • Single 3 3 ± 0.3V power supply • H ighspeed — 15 ns


    OCR Scan     		7c1399: CY7C1399 CY7C1399 PDF