PLL2073X Search Results

PLL2073X Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
PLL2073X		Samsung Electronics	Phase-Locked Loop (PLL) frequency		Original	PDF

PLL2073X Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
20MHZ Abstract: 300MHZ PLL2073X Text: 20MHz ~ 300MHz FSPLL PLL2073X Ver 1.5_5 General Description The pll2073x is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency FOUT is related to the	Original	20MHz 300MHz PLL2073X pll2073x 120ps 300MHz 120uA) 120uA 220uA) 20MHZ	PDF
samsung electrolytic capacitor Abstract: frequency divider block diagram SAMSUNG DATASHEET CHIP CAPACITOR PLL2073X SAMSUNG CHIP CAPACITOR Text: PLL 6 Contents PLL2073X . 6-1 PLL2073X General Description Features The PLL2073X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on a	Original	PLL2073X PLL2073X 20MHz 300MHz 120ps STD131 samsung electrolytic capacitor frequency divider block diagram SAMSUNG DATASHEET CHIP CAPACITOR SAMSUNG CHIP CAPACITOR	PDF
samsung electrolytic capacitor Abstract: "Frequency Divider" 20mhz xtal PLL2073X STD130 104 ceramic capacitor Text: PLL 6 Contents PLL2073X . 6-1 PLL2073X General Description Features The PLL2073X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on a	Original	PLL2073X PLL2073X 20MHz 300MHz 120ps STD130 samsung electrolytic capacitor "Frequency Divider" 20mhz xtal STD130 104 ceramic capacitor	PDF
AO211 Abstract: IX 3354 AO222 ND2D2 Text: Revision History Based on Hard Copy . - First Edition(V1.0) : June 2001 • Chapter 1 : Introduction(V1.0) • Chapter 2 : DC Electrical Characteristics(V1.1) • Chapter 3 : Internal Macrocells(V2.1) • Chapter 4 : Input/Output Cells(V2.1) • Chapter 5 : Compiled Macrocells(V1.1)	Original	STD131 AO211 IX 3354 AO222 ND2D2	PDF
MX2D2 Abstract: OA2111 AO222 AO211 STD130 CHAPTER 1 Introduction to Power Semiconductors standard cell library samsung soc Text: Revision History Based on Hard Copy . - First Edition(V1.0) : June 2001 • Chapter 1 : Introduction(V1.0) • Chapter 2 : DC Electrical Characteristics(V1.1) • Chapter 3 : Internal Macrocells(V2.1) • Chapter 4 : Input/Output Cells(V2.1) • Chapter 5 : Compiled Macrocells(V3.1)	Original	STD130 MX2D2 OA2111 AO222 AO211 STD130 CHAPTER 1 Introduction to Power Semiconductors standard cell library samsung soc	PDF
TDA 9361 PS Abstract: tda 2974 LD5Q ci 8602 gn block diagram TDA 2265 5.1 AUDIO AMP TDA 2030 TDA 7877 TDA 0200 circuit TDA 9594 TDA 2088 Text: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device	Original	STD130 STD130 24nW/MHz ARM920T/ARM940T, TDA 9361 PS tda 2974 LD5Q ci 8602 gn block diagram TDA 2265 5.1 AUDIO AMP TDA 2030 TDA 7877 TDA 0200 circuit TDA 9594 TDA 2088	PDF