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    PLCC32P Price and Stock

    Amphenol Corporation PLCC-32P-T-SMT-TR

    CONN PLCC SCKT SKT 32 POS 1.27MM SLDR ST SMD - Tape and Reel (Alt: PLCC-32P-T-SMT-TR)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas PLCC-32P-T-SMT-TR Reel 3,900
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    Amphenol Corporation PLCC-32P-T-SMT

    CONN PLCC SCKT SKT 32 POS 1.27MM SLDR ST SMD - Rail/Tube (Alt: PLCC-32P-T-SMT)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas PLCC-32P-T-SMT Tube 1,456
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    Jameco Electronics PLCC-32P-T-SMT Each 7,492 1
    • 1 $0.59
    • 10 $0.49
    • 100 $0.35
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    Amphenol FCi PLCC-32P-T-SMT

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    Bristol Electronics PLCC-32P-T-SMT 5,519 7
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    • 100 $0.4875
    • 1000 $0.21
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    PLCC-32P-T-SMT 229
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    Quest Components PLCC-32P-T-SMT 1,110
    • 1 $0.6
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    PLCC-32P-T-SMT 157
    • 1 $0.6
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    • 100 $0.4
    • 1000 $0.28
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    Amphenol FCi PLCC-32P-T-SMT-TR

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics PLCC-32P-T-SMT-TR 4,837 7
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    • 10 $0.75
    • 100 $0.4875
    • 1000 $0.21
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    PLCC-32P-T-SMT-TR 105
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    PLCC-32P-T-SMT-TR 100 7
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    • 10 $0.75
    • 100 $0.4875
    • 1000 $0.4875
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    Chip 1 Exchange PLCC-32P-T-SMT-TR 268
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    Component Electronics, Inc PLCC-32P-T-SMT-TR 163
    • 1 $1.54
    • 10 $1.54
    • 100 $1.15
    • 1000 $1
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    Amphenol FCi PLCC-32P-T

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    Bristol Electronics PLCC-32P-T 2,423
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    PLCC-32P-T 306
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    Quest Components PLCC-32P-T 1,303
    • 1 $1.275
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    • 100 $0.3825
    • 1000 $0.3315
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    PLCC-32P-T 627
    • 1 $1.275
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    • 100 $0.6375
    • 1000 $0.51
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    PLCC-32P-T 334
    • 1 $1.275
    • 10 $1.275
    • 100 $0.6375
    • 1000 $0.51
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    PLCC-32P-T 244
    • 1 $3.36
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    • 100 $2.24
    • 1000 $2.072
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    PLCC-32P-T 28
    • 1 $0.765
    • 10 $0.6375
    • 100 $0.459
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    Find more PLCC32P price and stock on Findchips.com

    PLCC32P Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Type PDF
    PLCC-32-P-T FCI Framatome Over 600 obsolete distributor catalogs now available on the Datasheet Archive - Sockets, PLCC thru-hole,#ofleads 32 Scan PDF
    PLCC-32P-T-SMT FCI Framatome Over 600 obsolete distributor catalogs now available on the Datasheet Archive - Sockets, PLCC surface mount,#ofleads 32 Scan PDF

    PLCC32P Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CMOS ASYNCHRONOUS FIFO 32 PIN

    Abstract: LH540202 32-PIN
    Text: LH540202 CMOS 1024 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words. It


    Original     		PDF LH540202 LH540202 32PLCC 32-pin, 450-mil 28-pin, 300-mil DIP28-W-300) CMOS ASYNCHRONOUS FIFO 32 PIN 32-PIN

    LH5492

    Abstract: 32-PIN
    Text: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based


    Original     		PDF LH5492 32PLCC-1 32-pin, 450-mil 32-pin PLCC32-P-R450-PED) LH5492U-25 5492MD LH5492

    LH540203

    Abstract: LH5498 32-PIN
    Text: LH540203 CMOS 2048 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It


    Original     		PDF LH540203 LH540203 32PLCC 32-pin, 450-mil 28-pin, 300-mil DIP28-W-300) LH5498 32-PIN

    hcl l54

    Abstract: t538 LM3935 TXC7A dr3 c502 7A14300038 T596 quanta b30 c300 - 1 South Bridge ALI M1535
    Text: 5 4 3 2 1 Model MODEL REV MK3 M/B BOARD 1A 2A CHANGE LIST MK3 M/B BOARD Page FM 1 1A 2 3A PAGE 8 Layout change add R420,R423 for U25 OSC32K,Y3 BOM del 3 3B PAGE11 Layout change add C648 for HWPG,U5 and TC1&D2 BOM del First Release PAGE 2 Layout change add U37,R411,R412,R413,R414,R415,C647 for AMD recommand


    Original     		PDF OSC32K PAGE11 PAGE12 PAGE13 PAGE15 PAGE16 PAGE17 C620for 102K/F 1U/25V hcl l54 t538 LM3935 TXC7A dr3 c502 7A14300038 T596 quanta b30 c300 - 1 South Bridge ALI M1535

    ICS954206A

    Abstract: realtek 8110 cpu c644 100v 27p 31CT3MB0015 Socket AM2 quanta 31CT3MB0031 Quanta CT3 A06402 quanta ct1
    Text: 5 4 3 2 1 Model MODEL REV CT3/5 MB D 1A 31CT3MB0015 31CT3MB0031 CHANGE LIST Page PAGE 2 - Enable CLK48M from clokc generator for the PLL circuit of 7411, and disable the ocsillator circuit of PCI7411 PLL. PAGE 3 - Remove H/W shutdown circuit that supported ADM1032.


    Original     		PDF 31CT3MB0015 31CT3MB0031 CLK48M PCI7411 ADM1032. PC250 330U/2 PR251 PC251 1U/16V ICS954206A realtek 8110 cpu c644 100v 27p Socket AM2 quanta 31CT3MB0031 Quanta CT3 A06402 quanta ct1

    SW1010C

    Abstract: tipl22 b10 45g BD3 c502 diode "Z3M" PA6 MD35 quanta CH2506E PA6 MD40 "Digital isolation Barrier" modem
    Text: 5 4 3 2 1 ET2T SYSTEM BLOCK DIAGRAM PCI .CLOCK CK-GEN AMD Processor Socket A DC/DC ICS950902 P3,4 Max1632,Max1717 P2 D 5V,3V,CPUCORE VCC etc. P23 INTA#(VGA) DDR DIMM Twister-K NB VT8372 S3 Savage8 P11 CRT P16 LCD/INV CONN LVDS P17 H/W MONITOR 200/266MHZ


    Original     		PDF ICS950902 Max1632 Max1717 VT8372 266MB/s 200/266MHZ VT8235 OZ6912 TSB43AB21 15mil SW1010C tipl22 b10 45g BD3 c502 diode "Z3M" PA6 MD35 quanta CH2506E PA6 MD40 "Digital isolation Barrier" modem

    high level block diagram for asynchronous FIFO

    Abstract: DIP28-W-300 LH540202 LJH540202
    Text: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based onfully-staticCMOSdual-portSRAM tech­ nology, capable of storing up to 1024 nine-bit words. It


    OCR Scan     		PDF LH540202 LH5497 ArrVIDT/MS7202 LH5497H 28-Pin, 300-mil 32-Pin 32PLCC high level block diagram for asynchronous FIFO DIP28-W-300 LH540202 LJH540202

    32-PIN

    Abstract: LH540202
    Text: SHARp ^ blE ]> • i w ^ / m o m ô i a Q ? DG1D1MD 6Bb « S R P J /no p r e li m i n a r y I / U 4 - CMOS 5 1 2 x 9 / 1 0 2 4 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-ln, First-Out mem­


    OCR Scan     		PDF S1SD71S D010140 CMOS512x9/1024x9 LH5496/97 Am/IDT/MS7201/02 28-Pin, 300-mil 600-mil 32-PIN LH540202

    LH5498

    Abstract: No abstract text available
    Text: LH5498 FEATURES • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS 32-PIN PDIP TOP VIEW W C Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags


    OCR Scan     		PDF LH5498 28-Pin, 300-mil 600-mil 32-Pin IDT7203 5498-1D LH5498

    Untitled

    Abstract: No abstract text available
    Text: LH5492 4 K x 9 Clocked FIFO FEATURES status output signals are synchronized to these clocks, to simplify system design. The input and output ports oper­ ate altogether independently of each other, except when the FIFO becomes either totally full or else totally empty.


    OCR Scan     		PDF LH5492 32-Pin PLCC32-P-R450-PED) 32-pin, 450-mil LH5492U-25

    Untitled

    Abstract: No abstract text available
    Text: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory


    OCR Scan     		PDF LH540204 LH540204 32-pin, 450-mil 28-pin, 300-mil DIP28-W-300)

    Untitled

    Abstract: No abstract text available
    Text: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 5 1 2 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth W C 1• 28 —I ^ c c


    OCR Scan     		PDF LH5496/96H 28-Pin, 300-mil 600-mil 32-Pin IDT7201 LH5496/96H 32-pin, 450-mil

    Untitled

    Abstract: No abstract text available
    Text: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory


    OCR Scan     		PDF LH540204 LH540204 32-pin, 450-mil 28-pin, 300-mil DIP28-W-300)

    Untitled

    Abstract: No abstract text available
    Text: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns The LH540204 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 4096 nine-bit words. It


    OCR Scan     		PDF LH540204 LH5499 Am/IDT/MS7204 28-Pin, 300-mil 32-Pin LH540204

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY LH540203 CMOS 2048 X 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely


    OCR Scan     		PDF LH540203 LH5498 Am/IDT/MS7203 28-Pin, 300-mil 600-mil 32-Pin

    Untitled

    Abstract: No abstract text available
    Text: CMOS 1 K x 9 FIFO TO P V IEW 28-PIN PDIP • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write w C 1« 28 Dg C 2 27 □ d3 3 26 □ d5 C o • Fast Access Times: 15 720/25/35/50/65/80 ns PIN CONNECTIONS LJ < o FEATURES d. o2 C 4 25 ZI De


    OCR Scan     		PDF 28-Pin, 300-mil 600-mil 32-Pin IDT7202 LH5497/97H TaLH5497/97H LH5497/97H

    Untitled

    Abstract: No abstract text available
    Text: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based


    OCR Scan     		PDF LH5492 32-Pin 32PLCC PLCC32-P-R450-PED) 32-pin, 450-mil LH5492 LH5492U-25

    Untitled

    Abstract: No abstract text available
    Text: LH5493 FEATURES • Fast Cycle Times: 30/35 ns Frequency: 33/28.5 MHz • Parallel Data In; Serial Data and/or Parallel Data Out • Serial Input and Serial Shift Capability in Output Register, for Long-Word-Length Parallel-to-Serial Operations • Read Enable input and Two Write Enable


    OCR Scan     		PDF LH5493 32-Pin LH5493S 18-bit PLCC32-P-R450) LH5493U-25 5493MD

    Untitled

    Abstract: No abstract text available
    Text: LH5499 FEATURES CMOS 4K x 9 FIFO PIN CONNECTIONS • Fast Access Times: 20/25/35/50/65/80 ns • Full CMOS Dual Port Memory Array W C • Fully Asynchronous Read and Write • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Read Retransmit Capability


    OCR Scan     		PDF LH5499 28-Pin, 600-mil 32-Pin IDT7204 28-PIN 5499-ID LH5499 S4S9-20

    QE RTB

    Abstract: lh5497
    Text: LH5497 FEATURES • • • • • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS 28-PIN PDIP TOP VIEW w C Full C M O S Dual Port Memory Array Fully Asynchronous Read and Write Expandable in Width and Depth 1• 28 H v cc Dg C 2 27 □ d4


    OCR Scan     		PDF LH5497 28-Pin, 300-mil 600-mil 32-Pin IDT7202 28-PIN QE RTB lh5497

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY LH540203 C M O S 2048 X 9 A sy n ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It


    OCR Scan     		PDF LH540203 LH5498 Am/IDT/MS7203 28-Pin, 300-mil 600-mil 32-Pin

    Untitled

    Abstract: No abstract text available
    Text: LH540201/02 PRELIMINARY CMOS 512 x 9 /1 0 2 4 x 9 A syn ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-In, First-Out mem­ ory device, based on fully-static CMOS dual-port SRAM


    OCR Scan     		PDF LH540201/02 LH5496/97 Am/IDT/MS7201/02 28-Pin, 300-mil 600-mil 32-Pin

    Untitled

    Abstract: No abstract text available
    Text: LH5497/97H FEATURES • • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 1 K x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW WC Full CMOS Dual Port Memory Array 1• 28 □ V CC DS C 2 27 □ d4 D a li 3 26 3 d5 • Fully Asynchronous Read and Write Dj C


    OCR Scan     		PDF LH5497/97H 28-Pin, 300-mil 600-mil 32-Pin IDT7202 28-PIN 5497/97H

    32PLCC

    Abstract: No abstract text available
    Text: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing


    OCR Scan     		PDF LH540202 LH5497 Am/IDT/MS7202 LH5497H 28-Pin, 300-mil 300-miis0j* 32-Pin 32-pin, 32PLCC