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    Kyocera AVX Components TCTPL1A226M8R

    CAP TANT 22UF 20% 10V 0805
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    DigiKey TCTPL1A226M8R Cut Tape 6,705 1
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    TCTPL1A226M8R Digi-Reel 6,705 1
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    Littelfuse Inc V14E275PL1A

    VARISTOR 430V 6KA DISC 14MM
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    Littelfuse Inc V20H250PL1A

    VARISTOR 390V 10KA DISC 20MM
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    Ozdisan Elektronik V20H250PL1A
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    Sager V20H250PL1A 2,000
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    Littelfuse Inc V10H115PL1A

    VARISTOR 180V 3.5KA DISC 10MM
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    Sager V10H115PL1A 5,000
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    Littelfuse Inc V14H300PL1A

    VARISTOR 470V 6.5KA DISC 14MM
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    Sager V14H300PL1A 3,200
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    PL1A Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    00XXX001

    Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
    Text: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic


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    OR3T20 OR3T30 1A-06. OR3T80 00XXX001 BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12 PDF

    OR3LP26B

    Abstract: OR3T20 ORT8850 7ba2 diode pb7d
    Text: Preliminary Data Sheet April 2001 PayloadPlus /APC UTOPIA Slave Bridge Introduction Features The PayloadPlus/ATM port controller APC universal test and operations PHY interface for ATM (UTOPIA) slave bridge, also known as the PayloadPlus APC wedge (PAW) or the Atlanta™ interface


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    OR3T20 DS01-212NCIP OR3LP26B ORT8850 7ba2 diode pb7d PDF

    LCMXO2-1200HC-4TG100C

    Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
    Text: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1


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    HB1010 LCMXO2-1200HC-4TG100C LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC PDF

    Untitled

    Abstract: No abstract text available
    Text: ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM EMULATED EEPROM , CAN 2.0B AND J1850 BLPD PRELIMINARY DATA • Memories – Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E 3 TM (Emulated EEPROM)


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    ST92F124/ST92F150/ST92F250 8/16-BIT J1850 14x14 TQFP64 PDF

    CONTROLLER

    Abstract: speed control of three phase ac induction motor 3 phase ac Induction motor speed controller ic SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 220v dc motor speed control circuit 220v DC MOTOR SPEED CONTROLLER 220v DC MOTOR SPEED CONTROLLER schematic cmos XOR schmitt trigger pwm based bidirectional dc motor speed SCHEMATIC 12 to 220v inverter
    Text: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%


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    ST92141 8/16-BIT 32-pin 34-pin CONTROLLER speed control of three phase ac induction motor 3 phase ac Induction motor speed controller ic SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 220v dc motor speed control circuit 220v DC MOTOR SPEED CONTROLLER 220v DC MOTOR SPEED CONTROLLER schematic cmos XOR schmitt trigger pwm based bidirectional dc motor speed SCHEMATIC 12 to 220v inverter PDF

    Untitled

    Abstract: No abstract text available
    Text: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC August 2004 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists


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    ORLI10G 10Gbps 125Gbps, ORLI10G OIF-SFI4-01 16-bit ORLI10G-2BMN680I PDF

    ST92141

    Abstract: ST92E141 ST92P141 ST92T141 electronic tubes
    Text: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%


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    ST92141 8/16-BIT 32-pin ST92141 ST92E141 ST92P141 ST92T141 electronic tubes PDF

    IC TTL 7495 diagram and truth table

    Abstract: BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc
    Text: Data Sheet June 1999 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    DS99-087FPGA DS98-163FPGA-01) IC TTL 7495 diagram and truth table BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc PDF

    PT35c transistor

    Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic
    Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■


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    16-bit OR3L165B OR3L225B OR3L165B7PS208I-DB OR3L165B7PS240I-DB OR3L165B7BA352I-DB OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB OR3L225B7BM680I-DB PT35c transistor pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic PDF

    Untitled

    Abstract: No abstract text available
    Text: ST92163 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal Memories: 20 Kbytes ROM/EPROM/ OTP, 2 Kbytes RAM


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    ST92163 8/16-BIT PDF

    SS 1091 asn

    Abstract: TDA 1045 picture in picture chip SAE-J1850
    Text: ST92F120 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD PRELIMINARY DATA • ■ ■ ■ Memories – Internal Memory: up to 128 Kbytes Single Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte emulated EEPROM E3PROMTM – 224 general purpose registers (register file)


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    ST92F120 8/16-BIT J1850 SS 1091 asn TDA 1045 picture in picture chip SAE-J1850 PDF

    MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR

    Abstract: nb 358 d
    Text: ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM EMULATED EEPROM , CAN 2.0B AND J1850 BLPD PRELIMINARY DATA • Memories – Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)


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    ST92F124/ST92F150/ST92F250 8/16-BIT J1850 TQFP64 14x14 PQFP100 14x20 TQFP100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR nb 358 d PDF

    DAP 015

    Abstract: No abstract text available
    Text: ST92F120 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD DATASHEET • ■ ■ ■ Memories – Internal Memory: up to 128 Kbytes Single Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte emulated EEPROM E3PROMTM – 224 general purpose registers (register file)


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    ST92F120 8/16-BIT J1850 DAP 015 PDF

    7476 3 bit ripple counter

    Abstract: 7464 shift register marking code IAM SDIP32 SDIP42 ST92186B fsa10as
    Text: ST92186B 8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 32K ROM AND ENHANCED ON-SCREEN-DISPLAY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register file based 8/16 bit Core Architecture with RUN, WFI, and HALT modes -10 to 70°C Operating Temperature Range


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    ST92186B 8/16-BIT 250ns 165ns 32-pin 42-pin SDIP42) SDIP32) 7476 3 bit ripple counter 7464 shift register marking code IAM SDIP32 SDIP42 ST92186B fsa10as PDF

    Untitled

    Abstract: No abstract text available
    Text: ST92163R4 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT NOT FOR NEW DESIGN • ■ ■ s t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr


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    ST92163R4 8/16-BIT PDF

    1-256 demultiplexer

    Abstract: No abstract text available
    Text: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC November 2003 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the


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    ORLI10G 10Gbps 125Gbps, ORLI10G OIF-SFI4-01 16-bit ORLI10G-3BM680C ORLI10G-2BM680C ORLI10G-1BM680C 1-256 demultiplexer PDF

    PT15D

    Abstract: OR2T40A-6PS208I R4C18
    Text: Data Sheet August 2002 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology


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    16-bit 32-bit OR2T10A OR2T15A OR2T15B OR2T26A OR2T40A OR2T40B DS99-094FPGA DS98-022FPGA) PT15D OR2T40A-6PS208I R4C18 PDF

    vhdl code for pcm bit stream generator

    Abstract: No abstract text available
    Text: Preliminary Data Sheet January 2002 ORCA ORT4622 Field-Programmable System Chip FPSC Four-Channel x 622 Mbits/s Backplane Transceiver Introduction Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for


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    ORT4622 432-Pin BC432 680-Pin BM680 DS00-110FPGA vhdl code for pcm bit stream generator PDF

    BA 5979

    Abstract: br06 lm 398- SAMPLE AND HOLD OR3T125 OR3T20 OR3T30 OR3T55 PT10 diagram for 3 bits binary multiplier circuit ic 7490 truth table
    Text: Data Sheet March 2002 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in


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    PDF

    3 phase ac Induction motor speed controller ic

    Abstract: 220v DC MOTOR SPEED CONTROLLER schematic 220v DC MOTOR SPEED CONTROLLER 3 phase induction motor 3 phase soft start induction motor principal dc motor control circuit 220v dc gate driver for control motor ac 3-phase tacho generator SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 3 phase pwm signal generator ic
    Text: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%


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    ST92141 8/16-BIT 32-pin 34-pin 3 phase ac Induction motor speed controller ic 220v DC MOTOR SPEED CONTROLLER schematic 220v DC MOTOR SPEED CONTROLLER 3 phase induction motor 3 phase soft start induction motor principal dc motor control circuit 220v dc gate driver for control motor ac 3-phase tacho generator SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 3 phase pwm signal generator ic PDF

    TV RADIO IC free

    Abstract: bf194 BD124 BF195 BD116 BF180 BFW87 BF196 BD133 BF197
    Text: 54 T ran sisto rs Continued Electronic Valves Z & I Aero Services Ltd London England 1972-73 ^JapìiX Notes T03 15W 30m c 1t +80 T03 45W 95m cl2i +60 55<2 2A 1A BD123 BD124 S/NPN S/NPN T03 MD17 45W 15W 85m c<2) 60m cm +90 +70 55<2) 60‘2’ 1A 0 .5A BD131


    OCR Scan
    BD116 BD121 95mcl2i BD123 85mc121 BF196 250mW 400mcl2t 39dbl3> BF197 TV RADIO IC free bf194 BD124 BF195 BF180 BFW87 BD133 PDF

    ST90R91

    Abstract: st90r9
    Text: SGS-THOMSON ¡y ST90R91 ROMLESS HCMOS MCU WITH BANKSWITCH _ AND A/D CONVERTER PRELIMINARY DATA Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time : 500ns 12MHz internal ROMIess to allow maximum external memory


    OCR Scan
    ST90R91 500ns 12MHz PQFP80 80-pin ST90R91Q 68-pin ST90R91C PLCC68) QFP80 ST90R91 st90r9 PDF

    Untitled

    Abstract: No abstract text available
    Text: AT&T Data Sheet October 1995 Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 |im technology (four-input look-up table delay less than 3.6 ns)


    OCR Scan
    ATT2C04, ATT2C06, ATT2C08, ATT2C10, ATT2C12, ATT2C15, ATT2C26, ATT2C40. DS95-183FPGA DS95-031 PDF

    HLX quartz

    Abstract: ST6398 98 UTA ING LA 76811 LM 76811 ST90 xckp CQFP80 PLCC84 PQFP80
    Text: 7 7 SGS-THOMSON 'JM, DfflDim@II[L[gOTa@raD g§ ST90158 - ST90135 8/16-BIT MCU FAMILY W ITH 16 to 64K ROM and 512 to 2K RAM P R E L IM IN A R Y D A T A • Register File based 8/16 bit Core Architecture with RUN, W FI, SLOW and HALT modes ■ 0 - 1 6 MHz Operation @ 5V±10%


    OCR Scan
    ST90158 ST90135 8/16-BIT 250ns 16MHz 16-bit 375ns 6/24/32/48/64K 80-PIN HLX quartz ST6398 98 UTA ING LA 76811 LM 76811 ST90 xckp CQFP80 PLCC84 PQFP80 PDF