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    PHYSICAL LAYER INTERFACE PROCESSOR Search Results

    PHYSICAL LAYER INTERFACE PROCESSOR Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S559FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3 / Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S141AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation

    PHYSICAL LAYER INTERFACE PROCESSOR Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    te-5005

    Abstract: TXC oscillator Npi pulse transformer ic 7217 DP83924BVCE tp link schematic TL 722 DP83924A
    Text: DP83924B DP83924B Quad 10 Mb/s Ethernet Physical Layer - 4TPHY Literature Number: SNLS033A DP83924BVCE Quad 10 Mb/s Ethernet Physical Layer - 4TPHY • Programmable MAC Interface supports most standard 7 signal MAC interfaces The DP83924B Quad 10Mbps Ethernet Physical Layer


    Original     		DP83924B DP83924B SNLS033A DP83924BVCE 10Mbps 10BASE-T. te-5005 TXC oscillator Npi pulse transformer ic 7217 tp link schematic TL 722 DP83924A PDF

    cwi 1011

    Abstract: No abstract text available
    Text: October 1994 DP83256 56-AP 57 PLAYER a TM Device FDDI Physical Layer Controller The DP83256 56-AP 57 Enhanced Physical Layer Controller (PLAYER a device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9 5 standard


    Original     		DP83256 56-AP DP83257VF VUL160A cwi 1011 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Serial RapidIO Physical Layer Interface User’s Guide October 2005 ipug26_02.0 Serial RapidIO Physical Layer Interface User’s Guide Lattice Semiconductor Introduction RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.


    Original     		ipug26 RIO-SERI-T42G5-N1. PDF

    GR-253-CORE

    Abstract: PM5358 PM5382 TSX 017
    Text: PM5358 S/UNI -4x622 Advance Quad Channel OC-12c ATM and POS Physical Layer Device FEATURES • Single chip quad ATM and POS UserNetwork Interface operating at 622 Mbit/s. • Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband


    Original     		PM5358 -4x622 OC-12c STS-12c GR-253-CORE PMC-2000331 GR-253-CORE PM5358 PM5382 TSX 017 PDF

    GR-253-CORE

    Abstract: PM5358 PM5382
    Text: PM5358 S/UNI -4x622 Advance Quad Channel OC-12c ATM and POS Physical Layer Device FEATURES • Single chip quad ATM and POS UserNetwork Interface operating at 622 Mbit/s. • Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband


    Original     		PM5358 -4x622 OC-12c STS-12c GR-253-CORE PMC-2000331 GR-253-CORE PM5358 PM5382 PDF

    ATM management SYSTEM abstract

    Abstract: CX28375 abstract of 24 hour timer CX28342 CX28343 CX28344 CX28346 CX28394 CX28395 CX28398
    Text: A CONEXANT BUSINESS Telecom Application Package PHY Software Products Physical Layer Device Interface Software The Telecom Application Package TAP from Mindspeed Technologies™ is “must-have” software that simplifies development for physical layer (PHY) devices. TAP software


    Original     		00070A M01-0351 ATM management SYSTEM abstract CX28375 abstract of 24 hour timer CX28342 CX28343 CX28344 CX28346 CX28394 CX28395 CX28398 PDF

    Untitled

    Abstract: No abstract text available
    Text: TNETE2101 10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE SPWS032D – JANUARY 1997 – REVISED MARCH 1999 D D D D D D Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to 10BASE-T, 100BASE-TX, and 100BASE-FX


    Original     		TNETE2101 10BASE-T/100BASE-TX/100BASE-FX SPWS032D 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/100BASE-TX RJ-45 22-A114-A PDF

    s-link

    Abstract: 100BASE-FX ST6118 TNETE2101 Self-Test Plan Wired Management Baseline
    Text: TNETE2101 10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE SPWS032D – JANUARY 1997 – REVISED MARCH 1999 D D D D D D Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to 10BASE-T, 100BASE-TX, and 100BASE-FX


    Original     		TNETE2101 10BASE-T/100BASE-TX/100BASE-FX SPWS032D 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/100BASE-TX RJ-45 22-A114-A s-link 100BASE-FX ST6118 TNETE2101 Self-Test Plan Wired Management Baseline PDF

    100BASE-FX

    Abstract: ST6118 TNETE2101
    Text: TNETE2101 10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE SPWS032D – JANUARY 1997 – REVISED MARCH 1999 D D D D D D Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to 10BASE-T, 100BASE-TX, and 100BASE-FX


    Original     		TNETE2101 10BASE-T/100BASE-TX/100BASE-FX SPWS032D 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/100BASE-TX RJ-45 22-A114-A 100BASE-FX ST6118 TNETE2101 PDF

    valor st6118

    Abstract: 100BASE-FX ST6118 TNETE2101
    Text: TNETE2101 10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE SPWS032D – JANUARY 1997 – REVISED MARCH 1999 D D D D D D Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to 10BASE-T, 100BASE-TX, and 100BASE-FX


    Original     		TNETE2101 10BASE-T/100BASE-TX/100BASE-FX SPWS032D 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/100BASE-TX RJ-45 22-A114-A valor st6118 100BASE-FX ST6118 TNETE2101 PDF

    open LVDS deserialization IP

    Abstract: DS243 crc verilog code 16 bit RAPIDIO
    Text: RapidIO 8-bit Port Physical Layer v3.0.2 DS243 February 10, 2005 Product Specification Introduction LogiCORE Facts The LogiCORE RapidIO Physical Layer Interface, a fixed-netlist solution for the RapidIO interconnect, is a pre-implemented and fully tested module for Xilinx


    Original     		DS243 2V1000FF896-4 2V2000FF896-4 2VP7FF896-5 2VP20F896modules open LVDS deserialization IP crc verilog code 16 bit RAPIDIO PDF

    taser

    Abstract: cops instrument display 0X00 PM7375 of op-amp LF 398 lf 10193
    Text: PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PM7375 TM LASAR155 LOCAL ATM SEGMENTATION AND REASSEMBLY & PHYSICAL LAYER INTERFACE DATA SHEET ISSUE 6: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE


    Original     		PM7375 LASAR-155 PMC-931127 PM7375 LASAR155 PMC-931123, taser cops instrument display 0X00 of op-amp LF 398 lf 10193 PDF

    RCA H 432

    Abstract: PM5384 radr GR-253-CORE 3G ATM "network interface cards"
    Text: PM5384 S/UNI 1x155 Released Single Channel OC-3c ATM and POS Physical Layer Device FEATURES • Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 155.52 Mbit/s. • Implements the ATM Forum User Network Interface UNI and the ATM


    Original     		PM5384 1x155 GR-253-CORE PMC-2011690 RCA H 432 PM5384 radr GR-253-CORE 3G ATM "network interface cards" PDF

    MDIO clause 45 specification

    Abstract: MDIO clause 45 MDIO vhdl code for ethernet csma cd vhdl code for ethernet mac spartan 3 vhdl code for mac interface Xilinx ISE Design Suite 9.2i ffs 642 verilog code for frame synchronization SPARTAN-6 mgt
    Text: XAUI v9.1 DS266 December 2, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.


    Original     		DS266 10-Gbps 10-Gigabit MDIO clause 45 specification MDIO clause 45 MDIO vhdl code for ethernet csma cd vhdl code for ethernet mac spartan 3 vhdl code for mac interface Xilinx ISE Design Suite 9.2i ffs 642 verilog code for frame synchronization SPARTAN-6 mgt PDF

    MDIO

    Abstract: MDIO clause 45 MDIO clause 45 specification vhdl code for mac interface 10GBASE-X datasheets of optical fpgas giga media converter 10GBASE-LX4 UCF virtex-4 ffs 642
    Text: XAUI v8.2 DS266 June 24, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.


    Original     		DS266 10-Gbps 10-Gigabit MDIO MDIO clause 45 MDIO clause 45 specification vhdl code for mac interface 10GBASE-X datasheets of optical fpgas giga media converter 10GBASE-LX4 UCF virtex-4 ffs 642 PDF

    CX28250TAP

    Abstract: No abstract text available
    Text: Telecom Application Package PHY Software Products Physical Layer Device Interface Software > K E Y F E AT U R E S > Fully documented API The telecom application package TAP from Mindspeed Technologies is “must-have” software that simplifies development for physical layer (PHY) devices. TAP software


    Original     		s4000 xxxx-BRF-001-A M04-xxxx CX28250TAP PDF

    1x10G

    Abstract: P802 PM5390 STM-64 STS-192 UNI-9953 64-bin 6464C
    Text: PM5390 S/UNI -9953 Advance 10 Gbit/s Physical Layer Device for POS, ATM and Ethernet FEATURES • Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Rec. I.432. • Implements the Point-to-Point Protocol


    Original     		PM5390 STS-48c STM-16-16c) STS-192 STM-64) STM-16c) STS-192c PMC-2000181 1x10G P802 PM5390 STM-64 STS-192 UNI-9953 64-bin 6464C PDF

    AX4000

    Abstract: PM3388 DDR2 sodimm pcb layout
    Text: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking Forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer


    Original     		PM3388 TN1121 OC-192 10Gbps PM-3388 PM-3388 1-800-LATTICE AX4000 PM3388 DDR2 sodimm pcb layout PDF

    IXF18101

    Abstract: ORSPI4-2FE1036C POWR1208 pDS4102-DL2A
    Text: SPI4.2 Interoperability Between ORSPI4 and LatticeSC Devices June 2006 Technical Note TN1116 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer


    Original     		TN1116 OC-192 TN1059, IXF1810 1-800-LATTICE IXF18101 ORSPI4-2FE1036C POWR1208 pDS4102-DL2A PDF

    Untitled

    Abstract: No abstract text available
    Text: PM7375 LASAR-155 DATA SHEET ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER :1 7: 06 AM PMC-931127 00 4 11 PM7375 ,2 TM fo fe fe fo n Mo nd ay ,0 3M ay LASAR155 DATA SHEET Do wn lo ad ed by ef we fe fe LOCAL ATM SEGMENTATION AND REASSEMBLY & PHYSICAL LAYER INTERFACE


    Original     		PM7375 LASAR-155 PMC-931127 PM7375 LASAR155 PMC-931123 PDF

    intellon p111

    Abstract: Intellon intellon p300 intellon p200 P300 SSC P200 EIA-600 p300ra SSC-P300 P111
    Text: Technical Data Sheet SSC P300 PL Network Interface Controller Features • Enables Low-cost CEBus compatible products • EIA-600 CEBus Data Link Layer services • EIA-600 Physical Layer transceiver • Spread Spectrum Carrier Power Line technology


    Original     		EIA-600 EIA-600 intellon p111 Intellon intellon p300 intellon p200 P300 SSC P200 p300ra SSC-P300 P111 PDF

    valor st6118

    Abstract: 1 a250 100BASE-FX TNETE2101
    Text: TNETE2101 10BASE-T/100BASE-TX/1OOBASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE • • ■ I I V • • • Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to 10BASE-T, 10OBASE-TX, and 10OBASE-FX


    OCR Scan     		TNETE2101 10BASE-T/1OOBASE-TX/1OOBASE-FX SPWS032B 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/1OOBASE-TX RJ-45 22-A114-A valor st6118 1 a250 TNETE2101 PDF

    str W 6553

    Abstract: No abstract text available
    Text: TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWSQ34 - MARCH 1998 Single-Chip Token-Ring Solution IBM Token-Ring Network™ Compatible Compatible With ISO/IEC IEEE Std 802.5:1992 Token-Ring Access-Method and Physical-Layer Specifications


    OCR Scan     		TI380C30A SPWSQ34 TI380FPA str W 6553 PDF

    100BASE-FX

    Abstract: TNETE2101
    Text: TNETE2101 10BASE-T/1OOBASE-TX/1OOBASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE S P W S 0 3 2 C -J A N U A R Y 1 9 9 7 -R E V IS E D N O VEM BER 1998 • • • • Integrated, Single-Chip, Ethernet Physical-Layer PHY Interface for Full-Duplex or Half-Duplex Connection to


    OCR Scan     		TNETE2101 10BASE-T/1OOBASE-TX/1OOBASE-FX SPWS032C-JANUARY 1997-REVISED 10BASE-T, 100BASE-TX, 100BASE-FX 10BASE-T/100BASE-TX RJ-45 22-A114-A TNETE2101 PDF