PHASE LOGIC LOOP Search Results

PHASE LOGIC LOOP Result Highlights (5)

Part	Manufacturer	Description
TB67B001BFTG	Toshiba Electronic Devices & Storage Corporation	Brushless Motor Driver/3 Phases Driver/Vout(V)=25/Iout(A)=3/Square Wave
TC78B011FTG	Toshiba Electronic Devices & Storage Corporation	Brushless Motor Driver/3 Phases Driver/Vout(V)=30/Square, Sine Wave
TB67S141AFTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface
TB67B001AFTG	Toshiba Electronic Devices & Storage Corporation	Brushless Motor Driver/3 Phases Driver/Vout(V)=25/Iout(A)=3/Square Wave
TB67H480FNG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ PHASE input type

PHASE LOGIC LOOP Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: T R I Q U I N T S E M I C O N D U C T O R, I N C . GA1110E Figure 1. Block Diagram VDD T1 CLKIN FBIN S1 S0 T0 GND 8 7 6 5 4 3 2 1 PHASE-LOCKED LOOP PLL PHASE CONTROL LOGIC Multi-Phase Clock Buffer MUX CONFIGURATION LOGIC Features GND OUTPUT BUFFER OUTPUT	Original	GA1110E GA1110E	PDF
CD54HC297 Abstract: CD74HCT297 CD54HC297F3A CD74HC297 CD74HC297E LH211 Text: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003	Original	HC297 HCT29 CD54HC297, CD74HC297, CD74HCT297 SCHS177B HC297 CD74HCT297 55MHz 35MHz CD54HC297 CD54HC297F3A CD74HC297 CD74HC297E LH211	PDF
Untitled Abstract: No abstract text available Text: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54HC297, CD74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177B High-Speed CMOS Logic Digital Phase-Locked Loop November 1997 - Revised May 2003	Original	HC297 HCT29 CD54HC297, CD74HC297, CD74HCT297 SCHS177B HC297 CD74HCT297 55MHz 35MHz	PDF
74hc297 application notes Abstract: SCHA002 HC297 74ls297 SCHA003 74HC297 Text: [ /Title CD74 HC297 , CD74 HCT29 7 /Subject (HighSpeed CMOS Logic Digital PhaseLocked CD54/74HC297, CD74HCT297 Data sheet acquired from Harris Semiconductor SCHS177A High-Speed CMOS Logic Digital Phase-Locked-Loop November 1997 - Revised May 2000 Features	Original	CD54/74HC297, CD74HCT297 SCHS177A HC297 CD74HCT297 dut1996) SDYA012 SN54/74HCT SCLA011 SCLA008 74hc297 application notes SCHA002 74ls297 SCHA003 74HC297	PDF
INTEL 845 MOTHERBOARD CIRCUIT diagram Abstract: 1N4148 ADP3120A ADP3188 intel 845 MOTHERBOARD pcb CIRCUIT diagram SUPPLY-ADP3190A 228nF Text: 6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller ADP3190 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±9.5 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external	Original	ADP3190 ADP3190 RQ-28) ADP3190JRUZ-RL ADP3190JRQZ-RL1 ADP3190AJRUZ-RL1 ADP3190AJRQZ-RL1 28-Lead INTEL 845 MOTHERBOARD CIRCUIT diagram 1N4148 ADP3120A ADP3188 intel 845 MOTHERBOARD pcb CIRCUIT diagram SUPPLY-ADP3190A 228nF	PDF
Digital Alarm Clock 40 pin Abstract: BLOCK diagram of light sensitive alarm application of light sensitive alarm RGR1551 diagram of light sensitive alarm Text: Fiber Optic “Light to Logic” Receiver with Clock Recovery Technical Data RGR1551 Features Applications • Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility • Long Reach, High Performance • Sensitivity –35 dBm end of life • Phase-Locked Loop (PLL)	Original	RGR1551 20-Pin RGR1551 5966-0456E Digital Alarm Clock 40 pin BLOCK diagram of light sensitive alarm application of light sensitive alarm diagram of light sensitive alarm	PDF
RGR2622 Abstract: No abstract text available Text: Fiber Optic “Light to Logic” Receiver with Clock Recovery Technical Data RGR2622 Features Description • Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility • Sensitivity –31 dBm • Phase-Locked Loop PLL Timing Recovery Circuit • Meets All SONET Jitter	Original	RGR2622 20-Pin RGR2622 5966-0457E	PDF
0491 Abstract: 1N4148WS ADP3110 ADP3110A ADP3186 NTD60N02 nichicon pw ad318 DAC 08080 desktop MOTHERBOARD CIRCUIT diagram Text: 5-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller ADP3186 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±1% worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high	Original	ADP3186 MO-137-AF 28-Lead RQ-28) ADP3186JRUZ-REEL ADP3186JRQZ-REEL1 D04914-0-3/06 0491 1N4148WS ADP3110 ADP3110A ADP3186 NTD60N02 nichicon pw ad318 DAC 08080 desktop MOTHERBOARD CIRCUIT diagram	PDF
LC030 Abstract: MC68040 MC88916 MC88916DW70 MC88916DW80 Nippon capacitors Text: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver With Processor Reset The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference	Original	MC88916 MC68/EC/LC030/040 80MHz. MC88916DW70 MC88916DW80, MC88916 BR1333 MC88916/D* MC88916/D LC030 MC68040 MC88916DW80 Nippon capacitors	PDF
23MLCC Abstract: ADP3418 Text: 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller ADP3168* FEATURES Selectable 2-, 3-, or 4-Phase Operation at up to 1 MHz per Phase ؎10 mV Worst-Case Differential Sensing Error over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers	Original	ADP3168* ADP3168 ADP3168 28-Lead RU-28) C03258 MO-153AE 23MLCC ADP3418	PDF
LC030 Abstract: MC68040 MC88920 Nippon capacitors Text: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver MC88920 With Power-Down/Power-Up Feature The MC88920 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference	Original	MC88920 MC88920 MC68/EC/LC030/040 MC88920/D* MC88920/D BR1333 LC030 MC68040 Nippon capacitors	PDF
Untitled Abstract: No abstract text available Text: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop	Original	SN74LV4046A SCES656C 000-V A114-A) A115-A)	PDF
MC68040 Abstract: MC88921 Nippon capacitors Text: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver MC88921 With Power-Down/Power-Up Feature The MC88921 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference	Original	MC88921 MC88921 MC88921/D* MC88921/D BR1333 MC68040 Nippon capacitors	PDF
ADP3181 Abstract: ADP3110 1N4148WS IPD06N03L IPD12N03L VRD10 RPH2 Text: 5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller ADP3181 FEATURES Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase ±14.5 mV worst-case mV differential sensing error over temperature Logic-level PWM outputs for interface to external high	Original	ADP3181 ADP3181JRU. VRD10 ADP3181JRQ) MO-137-AF 28-Lead RQ-28) ADP3181JRUZ-REEL ADP3181JRQZ-RL1, TSSOP--13" ADP3181 ADP3110 1N4148WS IPD06N03L IPD12N03L VRD10 RPH2	PDF

Untitled Abstract: No abstract text available Text: Rev 1; 4/08 100MHz HCSL Clock Oscillator The DS4100H is a low-jitter 100MHz clock oscillator with a high-speed current steering logic HCSL output. It combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5mm by 3.2mm ceramic package. Typical phase jitter is 0.9psRMS from	Original	100MHz DS4100H 12kHz 20MHz. 39ppm DS4100H	PDF
4046a Abstract: No abstract text available Text: [ /Title CD74 HC404 6A, CD74 HCT40 46A /Subject (HighSpeed CMOS CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Data sheet acquired from Harris Semiconductor SCHS204J High-Speed CMOS Logic Phase-Locked Loop with VCO February 1998 - Revised December 2003	Original	CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SCHS204J HC4046A HCT4046A CD4046B 4000B" 4046a	PDF
Untitled Abstract: No abstract text available Text: [ /Title CD74 HC404 6A, CD74 HCT40 46A /Subject (HighSpeed CMOS CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Data sheet acquired from Harris Semiconductor SCHS204J High-Speed CMOS Logic Phase-Locked Loop with VCO February 1998 - Revised December 2003	Original	HC404 HCT40 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SCHS204J 18MHz 12MHz HC4046A	PDF
Untitled Abstract: No abstract text available Text: [ /Title CD74 HC404 6A, CD74 HCT40 46A /Subject (HighSpeed CMOS CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Data sheet acquired from Harris Semiconductor SCHS204J High-Speed CMOS Logic Phase-Locked Loop with VCO February 1998 - Revised December 2003	Original	HC404 HCT40 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SCHS204J 18MHz 12MHz HC4046A	PDF
4000B Abstract: CD4046B CD54HC4046A CD54HCT4046A CD74HC4046A CD74HCT4046A HC4046A HCT4046A Text: [ /Title CD74 HC404 6A, CD74 HCT40 46A /Subject (HighSpeed CMOS CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Data sheet acquired from Harris Semiconductor SCHS204J High-Speed CMOS Logic Phase-Locked Loop with VCO February 1998 - Revised December 2003	Original	HC404 HCT40 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SCHS204J 18MHz 12MHz HC4046A 4000B CD4046B CD54HC4046A CD54HCT4046A CD74HC4046A CD74HCT4046A HCT4046A	PDF
AD820 Abstract: ADP3164 ADP3164JRU ADP3413 RU-20 TSSOP-20 3f3 ferrite material Text: a FEATURES ADOPT Optimal Positioning Technology for Superior Load Transient Response and Fewest Output Capacitors Complies with VRM 9.1 with Lowest System Cost 4-Phase Operation at up to 500 kHz per Phase Quad Logic-Level PWM Outputs for Interface to External High-Power Drivers	Original	ADP3164 20-Lead RU-20) C02484 AD820 ADP3164 ADP3164JRU ADP3413 RU-20 TSSOP-20 3f3 ferrite material	PDF
A3936SEDTR-T Abstract: A3936 A3936SED A3936SED-T A3936SEDTR Text: 3936 DMOS THREE-PHASE PWM MOTOR DRIVER ABSOLUTE MAXIMUM RATINGS at TA = +25°C Load Supply Voltage, VBB . 50 V Output Current, IOUT. ±3 A* Logic Supply Voltage, VDD . 7.0 V	Original		PDF
demodulation Abstract: Integrated Circuit PLL Text: MPV5 Series 9x14 mm, 5.0 Volt, PECL, VCXO • LVDS and PECL Output Logic With Good Integrated Jitter Performance 5 ps • Phase-Locked Loops (PLL’s), Clock Recovery, Reference Signal Tracking, Synthesizers, Frequency Modulation/ Demodulation OBSOLETE Pin Connections	Original		PDF
diode BY 399 itt Abstract: Q20P010 M/Q20P025 Text: DEVICE SPECIFICATION ECL/TTL “TURBO ” LOGIC ARRAYS WITH PHASE-LOCKED LOOP Q20P010/Q20P025 FEATURES On-chip high frequency phase-locked loop Up to 1.25 GHz capability Edge jitter as low as 50 ps pk-pk 900 and 3000 gates of customizable digital logic Utilizes proven Q20000* Series macro library	OCR Scan	Q20000* 10Ops TogP010 Q20P025 ii11n iiii111n Q20P010 Q20P025 0001b23 diode BY 399 itt M/Q20P025	PDF
Untitled Abstract: No abstract text available Text: LIE D AP PL IED MICRO C I R C U I T S DfiûTÜDe 0 0 0 1 BD 4 T71 « A f l C C ADVANCE INFORMATION Q20P001 ECL/TTL “TURBO” LOGIC ARRAY with PHASELOCKED LOOP FEATURES • Phase-Locked Loop On-Chip High Frequency Phase-Locked Loop r t : with external filter	OCR Scan	Q20P001 Q20000 Q20P010/Q20P025 15-Jan-93	PDF

PHASE LOGIC LOOP Search Results

PHASE LOGIC LOOP Result Highlights (5)

PHASE LOGIC LOOP Datasheets Context Search

Untitled

CD54HC297

Untitled

74hc297 application notes

INTEL 845 MOTHERBOARD CIRCUIT diagram

Digital Alarm Clock 40 pin

RGR2622

0491

LC030

23MLCC

LC030

Untitled

MC68040

ADP3181

Untitled

4046a

Untitled

Untitled

4000B

AD820

A3936SEDTR-T

demodulation

diode BY 399 itt

Untitled