AR-17
Abstract: AW12 Q110 Q117 RAM1024 scuba ar17
Text: ORCA Series 4 Quad-Port Embedded Block RAM August 2002 Technical Note TN1016 Introduction The ORCA Series 4 FPGA platform provides embedded block RAM EBR macrocells to compliment it’s distributed PFU RAM. By using ORCA Series 4 EBR, designers can realize the benefits of system-on-a- chip (SoC) and
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TN1016
512x18
AR-17
AW12
Q110
Q117
RAM1024
scuba
ar17
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AR-17
Abstract: AR17 AW16 br512 Q117 scuba AR17 datasheet AW12 Q014 transistor d115
Text: ORCA Series 4 Quad-Port Embedded Block RAM April 2002 Technical Note TN1016 Introduction The ORCA Series 4 FPGA platform provides embedded block RAM EBR macrocells to compliment it’s distributed PFU RAM. By using ORCA Series 4 EBR, designers can realize the benefits of system-on-a- chip (SoC) and intellectual property (IP) reuse to quickly deliver their end product to market. The ORCA EBR delivers several configurable blocks of memory based embedded IP. These blocks include quad-port RAM, dual-port RAM, FIFO memory,
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TN1016
512x18
AR-17
AR17
AW16
br512
Q117
scuba
AR17 datasheet
AW12
Q014
transistor d115
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Field-Programmable Gate Arrays
Abstract: MPC8260 MPC860
Text: Product Brief January 15, 2002 ORCA Series 4 Field-Programmable Gate Arrays Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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sink/12
256-Pin
352-Pin
416-Pin
432-Pin
680-Pin
PB02-027NCIP
PB01-046NCIP)
Field-Programmable Gate Arrays
MPC8260
MPC860
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ORT8850
Abstract: ORT8850H ORT8850L STM-64 STS-192
Text: Preliminary Product Brief May 2000 ORCA ORT8850 Field-Programmable System Chip Introduction Field-programmable system chips FPSCs bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Lucent Technologies Microelectronics Group
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ORT8850
ORT8850
PN00-071FPGA
ORT8850H
ORT8850L
STM-64
STS-192
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Field-Programmable Gate Arrays
Abstract: 416-PIN content addressable memory
Text: Product Brief June 2001 ORCA Series 4 Field-Programmable Gate Arrays Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:
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sink/12
PB01-046NCIP
PB00-011FPGA)
Field-Programmable Gate Arrays
416-PIN
content addressable memory
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ORT8850
Abstract: ORT8850H ORT8850L scrambling write operation using ram in fpga
Text: Product Brief July 2001 ORCA ORT8850 Field-Programmable System Chip FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Introduction Field-programmable system chips (FPSCs) bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single
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ORT8850
PB01-115NCIP
PB00-069FPGA)
ORT8850H
ORT8850L
scrambling
write operation using ram in fpga
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4-bit GTL to LVTTL transceiver
Abstract: digital clock using gates ORLI10G TRCV0110G TTRN0110G write operation using ram in fpga
Text: Product Brief February 2001 ORCA ORLI10G 10 Gbits/s Line Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable
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ORLI10G
ORLI10G
16-bit
PB01-048NCIP
PB01-021NCIP)
4-bit GTL to LVTTL transceiver
digital clock using gates
TRCV0110G
TTRN0110G
write operation using ram in fpga
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abstract 16-bit multiplexer using xilinx
Abstract: ATT ORCA fpga architecture CORE F5A FD1S3DX 4 leg push button switches cmos inv edit SR NOR latch MUX21
Text: Last Link Previous ORCA APPLICATION USER NOTES ispLEVER® version 3.0 For Use With ORCA 2002, and ispLEVER 2.0 and higher Technical Support Line: 1-800-LATTICE or 408-826-6002 international Next Last Link Previous Next Application Notes ispLEVER 3.0 IBM is a registered trademark of International Business Machines Corporation.
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1-800-LATTICE
abstract 16-bit multiplexer using xilinx
ATT ORCA fpga architecture
CORE F5A
FD1S3DX
4 leg push button switches
cmos inv
edit SR NOR latch
MUX21
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Untitled
Abstract: No abstract text available
Text: Product Brief January 15, 2002 ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125—3.5 Gbits/s 8B/10B SERDES Backplane Interface FPSC Introduction Lattice has developed a next-generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips SoC architecture, the
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ORT82G5
8B/10B
PB02-026
PB01-067NCIP)
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10G serdes 2.5 xaui
Abstract: infiniband PHY ORT82G5 STS-48 transponder chip OTN FPSC Lucent 10GMII
Text: Product Brief February 2001 ORCA ORT82G5 0.622/1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a next generation FPSC intended for highspeed serial backplane data transmission. Built on
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ORT82G5
PB01-067NCIP
PB01-047NCIP
10G serdes 2.5 xaui
infiniband PHY
STS-48
transponder chip OTN
FPSC Lucent
10GMII
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design a 4-bit arithmetic logic unit using xilinx
Abstract: OC192 ORLI10G TRCV0110G TTRN0110G 4-bit GTL to LVTTL transceiver
Text: Preliminary Product Brief November 2000 ORCA ORLI10G 10 Gbits/s Line Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a new ORCA Series 4 based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable
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ORLI10G
ORLI10G
16-bit
PB01-021NCIP
design a 4-bit arithmetic logic unit using xilinx
OC192
TRCV0110G
TTRN0110G
4-bit GTL to LVTTL transceiver
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write operation using ram in fpga
Abstract: No abstract text available
Text: Product Brief January 2002 ORCA ORT8850 Field-Programmable System Chip FPSC Eight-Channel x 850 Mbits/s Backplane Transceiver Introduction Field-programmable system chips (FPSCs) bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single
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680-Pin
BM680
352-Pin
BA352
ORT8850L
ORT8850H
ORT8850H/L
write operation using ram in fpga
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LCMX0640
Abstract: J-STD-012 LCMXO256C 3TN144C LATTICE 15 pin through hole d sub connector lcmx064
Text: MachXO Family Handbook Version 01.0, July 2005 MachXO Family Handbook Table of Contents July 2005 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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LCMX0640
J-STD-012
LCMXO256C
3TN144C LATTICE
15 pin through hole d sub connector
lcmx064
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BGA 927
Abstract: No abstract text available
Text: MachXO Family Handbook HB1002 Version 01.9, February 2007 MachXO Family Handbook Table of Contents February 2007 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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TN1089
TN1092
BGA 927
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MPC8260
Abstract: ORSO82G5 ORT82G5 STS-48
Text: Advance Product Brief October 2001 ORCA ORSO82G5 1.0—1.35/2.0—2.7 Gbits/s SONET Octal Backplane Interface FPSC Introduction Agere Systems Inc. has developed a next-generation FPSC intended for high-speed serial SONET backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips SoC
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PB01-165NCIP
MPC8260
ORT82G5
STS-48
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10Gb CDR
Abstract: 10GMII UNITED TECHNOLOGIES MICROELECTRONICS CENTER ORT82G5 STS-48 FPSC 020NC
Text: Preliminary Product Brief January 2001 ORCA ORT82G5 1.25/2.5/3.125 Gbits/s Backplane Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a next generation FPSC intended for highspeed serial backplane data transmission. Built on
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ORT82G5
PB01-047NCIP
PB01-020NCIP)
10Gb CDR
10GMII
UNITED TECHNOLOGIES MICROELECTRONICS CENTER
STS-48
FPSC
020NC
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PCLK40
Abstract: BGA 927
Text: MachXO Family Handbook HB1002 Version 02.0, November 2007 MachXO Family Handbook Table of Contents November 2007 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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TN1086
TN1090
TN1091
TN1092
PCLK40
BGA 927
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Untitled
Abstract: No abstract text available
Text: MachXO Family Handbook HB1002 Version 02.0, November 2007 MachXO Family Handbook Table of Contents November 2007 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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TN1092
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MachXO256
Abstract: MachXO sysIO Usage Guide
Text: MachXO Family Handbook HB1002 Version 01.7, November 2006 MachXO Family Handbook Table of Contents November 2006 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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TN1074
TN1089
TN1092
MachXO256
MachXO sysIO Usage Guide
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00XXX001
Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Text: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic
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OR3T30
1A-06.
OR3T80
00XXX001
BA 5979
R15C3
OR3T125
OR3T20
OR3T30
OR3T55
PT10
PT11
PT12
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BA 5979 S
Abstract: or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10
Text: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 m OR3C and 0.3 μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in
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OR3C804PS208I-DB
OR3C804BA352I-DB
OR3T206S208I-DB
OR3T306S208I-DB
OR3T306S240I-DB
OR3T306BA256I-DB
OR3T556PS208I-DB1
OR3T556S208I-DB
OR3T556PS240I-DB
OR3T556BA256I-DB
BA 5979 S
or3t806ba352-db
2764 EEPROM
BA 5979
BL06 transistor
OR3T125
OR3T20
OR3T30
OR3T55
PT10
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BA 5979 S
Abstract: how many pins in IC 4538 BA 5979 24 micro farad capacitor datasheet 3T80 transistor on 4409 AM 5766 ba 5412 PR25D or3t806ba352-db
Text: Data Sheet December 2002 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in
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OR3T806BC432I-DB
OR3T1256PS208I-DB
OR3T1256PS240I-DB
OR3T1256BA352I-DB
OR3T1256BC432I-DB
OR3T1256BC600I-DB
BA 5979 S
how many pins in IC 4538
BA 5979
24 micro farad capacitor datasheet
3T80
transistor on 4409
AM 5766
ba 5412
PR25D
or3t806ba352-db
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16X1 ram
Abstract: No abstract text available
Text: MachXO Family Handbook HB1002 Version 01.5, September 2006 MachXO Family Handbook Table of Contents September 2006 Section I. MachXO Family Data Sheet Introduction Features . 1-1
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TN1086
TN1074
16X1 ram
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Untitled
Abstract: No abstract text available
Text: JUN SO 1993 Product Brief April 1993 rm A T C T ^ ^ » M ic ro e le c tr o n ic s AT&T Optimized Reconfigurable Cell Array ORCA Series Field-Programmable Gate Arrays (FPGAs) Features • Identical and symmetrical programmable logic cells (PLCs) ■ 0.6 |im CMOS process technology
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PN93-030FPGA
PN93-017FPGA)
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