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    OTN TESTBENCH Search Results

    OTN TESTBENCH Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AD9554BCPZ-REEL7 Analog Devices Quad PLL Channel OTN & Multise Visit Analog Devices Buy
    AD9554/PCBZ Analog Devices Quad PLL Channel OTN & Mu Visit Analog Devices Buy
    AD9554BCPZ Analog Devices Quad PLL Channel OTN & Multise Visit Analog Devices Buy
    AD9554BCPZ-REEL Analog Devices Quad PLL Channel OTN & Multise Visit Analog Devices Buy
    AD9554-1BCPZ-REEL7 Analog Devices Quad PLL Channel OTN & Multise Visit Analog Devices Buy

    OTN TESTBENCH Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    OTU1

    Abstract: XIP2174 Paxonet Communications OC48 ISE4 OTN testbench
    Text: STS48 OTN Framer/Digital Wrapper CC381 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc381.ucf Testbench, test scripts Verification Tool


    Original     		PDF STS48 CC381) cc381 OTU1 XIP2174 Paxonet Communications OC48 ISE4 OTN testbench

    OTN testbench

    Abstract: CC481 XIP2196 OTU2 framer OC48 STS192 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder
    Text: STS192 OTN Framer/Digital Wrapper CC481 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc481.ucf Testbench, test scripts Verification Tool


    Original     		PDF STS192 CC481) cc481 OTN testbench XIP2196 OTU2 framer OC48 XILINX vhdl code REED SOLOMON encoder decoder vhdl code for bram Generic AIS verilog code for TCM decoder

    XIP2173

    Abstract: DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5 CC345
    Text: G.709-Compliant FEC Core CC345 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc345.ucf Testbench, test scripts Verification Tool Instantiation Templates


    Original     		PDF 709-Compliant CC345) cc345 XIP2173 DCM-1 dcm11 error correction code in vhdl verilog implementation of error correcting code application of optical encoder Reed-Solomon Decoder verilog code XC2V500-5

    OTU2 framer

    Abstract: verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL
    Text: CoreEl CC481 OTU2 Framer May 6, 2003 Product Specification AllianceCORE™ Facts separately Core Specifics See Table 1 Provided with Core Documentation User Guide, Design Guide EDIF netlist, NGC netlist Design File Formats Constraints Files cc481chp.ucf, cc481_wrap.ucf


    Original     		PDF CC481 cc481chp OTU2 framer verilog code for TCM decoder 8 BIT PROCESSOR USING VHDL

    rx data path interface in vhdl

    Abstract: vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler
    Text: CoreEl 1.25 Gb/s GFP Framer CC224 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC224 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		PDF CC224) CC224 apCC224 rx data path interface in vhdl vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler

    fpga vhdl code for crc-32

    Abstract: crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16
    Text: CoreEl CC327 10Gb GFP Framer May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com Features


    Original     		PDF CC327 OC-192 fpga vhdl code for crc-32 crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16

    PRBS-32

    Abstract: SystemVerilog AN-642-1 EP4CGX22BF14 AN6421 OTN testbench Stratix II GX FPGA Development Board Reference Manual
    Text: 2.5G Reed-Solomon II MegaCore Function Reference Design AN-642-1.0 Application Note The Altera 2.5G Reed-Solomon RS II MegaCore® function reference design demonstrates a basic application of the Reed-Solomon algorithm in data transmission between the Altera RS II encoder and decoder.


    Original     		PDF AN-642-1 PRBS-32 SystemVerilog EP4CGX22BF14 AN6421 OTN testbench Stratix II GX FPGA Development Board Reference Manual

    DVB smart card rs232 iris

    Abstract: fpga based 16 QAM Transmitter for wimax application with quartus fpga based 16 QAM Transmitter for wimax application EP4SGX230F1517 vhdl code for lte turbo decoder sodimm ddr3 connector PCB footprint starfabric eQFP 144 footprint higig2 SFP altera
    Text: Version 7.2 Altera Product Catalog Contents Glossary. 2 Stratix FPGA series. .3 HardCopy® ASIC series. 11 Arria® FPGA series. 15


    Original     		PDF

    v-by-one hs

    Abstract: camera-link to 3G-SDI converter Netlogic camera-link to HDMI converter camera-link to hd-SDI converter serdes hdmi optical fibre SFP CPRI EVALUATION BOARD AL460A verilog SATA HDMI verilog code
    Text: Version 8.0 Altera Product Catalog Contents Glossary. 2 Stratix FPGA series. .3 HardCopy® ASIC Series. 14 Arria® FPGA Series. 18


    Original     		PDF

    XAPP680

    Abstract: XC2VP20 fg676 hd-SDI deserializer LVDS lv114 parallel to serial conversion vhdl IEEE paper pcb layout mindspeed FF1152 FG256 XC2064 XC3090
    Text: RocketIO Transceiver User Guide UG024 v3.0 February 22, 2007 R R “Xilinx” and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are


    Original     		PDF UG024 XC2064, XC3090, XC4005, XC5210 XAPP680 XC2VP20 fg676 hd-SDI deserializer LVDS lv114 parallel to serial conversion vhdl IEEE paper pcb layout mindspeed FF1152 FG256 XC2064 XC3090

    verilog code for 2-d discrete wavelet transform

    Abstract: XAPP921c simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl umts simulink fpga based wireless jamming networks dvb-rcs chip XAPP569
    Text: XtremeDSP Solutions Selection Guide March 2008 INTRODUCTION Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35


    Original     		PDF

    vhdl code for DES algorithm

    Abstract: XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model verilog code for lms adaptive equalizer for audio LMS simulink 3SD1800A XILINX vhdl code REED SOLOMON encoder decoder fir filter with lms algorithm in vhdl code
    Text: XtremeDSP Solutions Selection Guide June 2008 Introduction Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35


    Original     		PDF