UPD70208H
Abstract: No abstract text available
Text: NEC ¿¿PD70208H, 70216H CONTENTS 1. PIN FUNCTIONS. 15 1.1 1.2 15 17 LIST OF PIN FUNCTIONS.
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uPD70208H
uPD70216H
PD70208H,
70216H
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Untitled
Abstract: No abstract text available
Text: NEC ,uPD70208, 70208 A , 70216, 70216 (A) CONTENTS 1. PIN FUNCTIONS. 14 1.1 LIST OF PIN FUNCTIONS.
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uPD70208
uPD70216
PD70208
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Untitled
Abstract: No abstract text available
Text: NEC A/PD70216 V50 16-Bit Microprocessor: High-Integration, CMOS NEC Electronics Inc. Description The /uPD70216 (V50T“) is a high-performance, lowpower 16-bit microprocessor integrating a number of commonly-used peripherals to dramatically reduce the size of microprocessor systems. The CMOS construc
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/PD70216
16-Bit
/uPD70216
/L/PD70216
PD70216
juPD70108//vPD70116
y/PD8086//uPD8088
9t30ZQd^
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PD70116
Abstract: PD71071C D71071 PD71071
Text: NEC ¿/PD71071 DMA Controller NEC Electronics Inc. Description The //PD71071 is a high-speed, high-perform ance d ire ct m em ory access DM A c o n tro lle r that provides high-speed data transfers between peripheral devices and m em ory. A program m able bus w id th allow s
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uPD71071
//PD71071
16-bit
PD71071
The/vPD71071
49-OOOS38C
49-000539B
-003760A
//PD71071
PD70116
PD71071C
D71071
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Untitled
Abstract: No abstract text available
Text: NEC . j j P D 7 10 7 1 NEC Electronics Inc. dm a c o n t r o lle r April 1987 Pin Configurations Description T he //PD71071 is a high-sp eed , h ig h -p e rfo rm an ce d ire ct m em ory a c c e s s D M A co n tro lle r that provides high -sp ee d data transfers between peripheral devices
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//PD71071
16-bit
48-Pin
juPD71071
L-000302
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uPD70216
Abstract: PD70208GF
Text: NEC /¿PD70208, 70208 A , 70216, 70216 (A) 18. RECOMMENDED SOLDERING CONDITIONS * This product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions for the surface mounting type, refer to the information document
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uPD70208
uPD70216
IEI-1207)
PD70208GF-X-3B9
80-pin
PD70216GF-X-3B9
PD70208GF
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d71071
Abstract: d70208 nec 529a MPD71071 UPD71071 70216 nec 70216 PD70208 D70116 d71071c
Text: NEC NEC Electronics Inc. jj P D 7 10 7 1 dm a c o n t r o lle r April 1987 D escriptio n Pin C o n fig u ratio n s The >uPD71071 is a high-speed, high -p e rfo rm a n ce d ire c t m em ory access D M A c o n tro lle r th a t provides high-speed data transfers between peripheral devices
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uPD71071
//PD71071
/PD71071
d71071
d70208
nec 529a
MPD71071
70216
nec 70216
PD70208
D70116
d71071c
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Untitled
Abstract: No abstract text available
Text: NEC /¿PD70208, 70208 A , 70216, 70216 (A) - NOTES FOR CMOS DEVICES-0 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must
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uPD70208
uPD70216
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D70216
Abstract: PD70208H-12 UPD70208H uPD70216 MPD70216 PD70208H
Text: NEC /¿PP70208H, 70216H 16. ELE C TR IC A L S P E C IFIC A TIO N S •Applied s ta n d a rd -The electrical characteristics shown below are applied to devices other than the old models conform ing
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PP70208H,
70216H
uPD70208H
uPD70216H-10
uPD70216H-12
uPD70216H-16
-A19/PS3
A8-A15
V40HL
D70216
PD70208H-12
uPD70216
MPD70216
PD70208H
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Untitled
Abstract: No abstract text available
Text: NEC li PP70208H, 70216H 8. REFU REFRESH CONTROL UNIT The REFU generates refresh cycles required for refreshing of external D R AM . Refresh enabling/disabling and the refresh interval can be set programmably. 8.1 FEATURES • Lowest-priority refreshing/highest-priority refreshing
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PP70208H,
70216H
16-bit
V40HL)
V50HL)
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nec v50
Abstract: nec 70216 00000H
Text: /¿PD70208,70208 A , 70216,70216 (A) NEC 2. MEMORY AND I/O CONFIGURATION 2.1 MEMORY SPACE The V40 and V50 can access a 1M-byte (512K-word) memory space. Figure 2-1. Memory Map FFFFFH Reserved FFFFCH FFFFBH Dedicated FFFFOH FFFEFH General Use 00400H 003FFH
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uPD70208
uPD70216
512K-word)
00400H
003FFH
00000H
PD70208,
PD70208
nec v50
nec 70216
00000H
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UPD70208H
Abstract: uPD70216H
Text: NEC /¿PD70208H, 70216H 2. MEMORY AND I/O CONFIGURATION 2.1 MEMORY SPACE The V40HL and V50HL can access a 1M-byte 512K-word memory space. Fig. 2-1 Memory Map FFFFFH Reserved FFFFCH FFFFBH Dedicated FFFFOH FFFEFH General Use 00400H 003FFH Interrupt Vector Table
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uPD70208H
uPD70216H
V40HL
V50HL
512K-word)
00400H
003FFH
V40HL
V50HL
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uPD71071
Abstract: No abstract text available
Text: NEC ¿¿PP70208H, 70216H 12. DMAU DMA CONTROL UNIT The DMAU has 4 DMA channels, and provides the functions (subset) o f tw o LSIs, the /iPD71071 and //PD71037. 12.1 FEATURES • Two operating modes (pPD71071 mode, /iPD71037 mode) • 20-bit address register
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PP70208H,
70216H
uPD71071
uPD71037
/iPD71037
20-bit
16-bit
/tPD71037
PD71071
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Untitled
Abstract: No abstract text available
Text: NEC //PD70208,70208 A , 70216,70216 (A) 10. SCU (SERIAL CONTROL UNIT) The SCU performs control of serial communication (asynchronous). Its functions are a subset of the /¿PD71051 excluding synchronous communication. Also, what was the control word register in the /¿PD71051 has been divided into two: a
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uPD70208
uPD70216
PD71051
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Untitled
Abstract: No abstract text available
Text: NEC /¿PD70208, 70208 A , 70216,70216 (A) 8. REFU (REFRESH CONTROL UNIT) The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh interval can be set programmably. 8.1 • • • FEATURES Lowest-priority refreshing/highest-priority refreshing
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uPD70208
uPD70216
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UPD70208H
Abstract: No abstract text available
Text: MPD70208H, 70216H NEC 11. ICU INTERRUPT CONTROL UNIT The ICU arbitrates among up to 8 interrupt requests {maskable interrupts) generated inside and outside the V40HL and V50HL, and transfers one o f them to the CPU. The ICU functions com prise the functions of the V40HL and V50HL
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uPD70208H
uPD70216H
V40HL
V50HL,
V50HL
V50HL.
PD71059
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UPD70208H
Abstract: V40HL PD70208H
Text: NEC ¿¿PD70208H, 70216H 15. INSTRUCTION SET Table 15-1 Operand Type Legend Description Identifier reg 8/16-bit general register destination register in an instruction using tw o 8/16-bit general registers reg' Source register in an instruction using tw o 8/16-bit general registers
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uPD70208H
uPD70216H
8/16-bit
16-bit
mem16
mem32
imm16
V40HL
PD70208H
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uPD71054
Abstract: No abstract text available
Text: NEC /JPP70208H, 70216H 9. TCU TIMER/COUNTER UNIT The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the //PD71054. 9.1 FEATURES • 3 x 16-bit counters • S ix programmable count m odes
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/JPP70208H,
70216H
uPD71054
16-bit
16programmable
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uPD71051
Abstract: No abstract text available
Text: NEC /¿PP70208H, 70216H 10. SCU SERIAL CONTROL UNIT The SCU perform s control of serial com m unication (asynchronous). Its functions are a subset o f the /iPD71051 excluding synchronous com m unication. Also, w hat was the control w ord register in the /iPD71051 has been divided
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PP70208H,
70216H
uPD71051
/iPD71051
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nec v40
Abstract: No abstract text available
Text: NEC /¿PD70208, 70208 A , 70216, 70216 (A) 4. CG (CLOCK GENERATOR) The CG generates a clock at a frequency of 112 that of the crystal and oscillator connected to the X1 and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output.
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uPD70208
uPD70216
nec v40
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Untitled
Abstract: No abstract text available
Text: NEC /¿PP70208,70208 A , 70216, 70216 (A) 12. DMAU (DMA CONTROL UNIT) The DMAU has 4 DMA channels, and is a subset of the //PD71071 12.1 FEATURES • • • • • • • • • • • • • 20-bit address register 16-bit count register Four independent DMA channels
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PP70208
uPD71071
20-bit
16-bit
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uPD71054
Abstract: No abstract text available
Text: NEC /IPP70208, 70208 A , 70216, 70216 (A) 9. TCU (TIMER/COUNTER UNIT) The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the /¿PD71054. 9.1 FEATURES • 3 x 16-bit counters • Six programmable count modes
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/IPP70208,
uPD71054
16-bit
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nec 4010
Abstract: No abstract text available
Text: NEC 1. ;uPD70208, 70208 A , 70216, 70216 (A) PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS Pin Name Function Input/Output ADO to AD15Noto1 3-state I/O Time-division address/data bus ADO to AD7Noto 2 3-state I/O Time-division address/data bus A8 to A15Note2 3-state output
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uPD70208
uPD70216
AD15Noto1
A15Note2
A16/PS0
A19/PS3
nec 4010
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bus arbitration
Abstract: uPD70216 UPD70208H
Text: NEC juPD70208H, 70216H 6. BAU BUS ARBITRATION UNIT The BAU perform s bus arbitration am ong bus masters. A list o f bus masters (units w hich can acquire the bus) is shown below. Table 6-1 Bus Masters Bus M aster Bus Cycle CPU Program fetch, data read/write
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uPD70208H
uPD70216H
V40HL
V50HL-internal
PD70208H,
70216H
V50HL
bus arbitration
uPD70216
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