Untitled
Abstract: No abstract text available
Text: NEC ¿¿PD70236A 13. STANDBY FUNCTIONS The nPD70236A is provided with two standby functions: Standby during program standby resulting from a HALT instruction, and standby during program execution resulting from switching the instruction cycle time. 13.1 FEATURES
|
OCR Scan
|
PDF
|
uPD70236A
nPD70236A
|
D70236A
Abstract: V53A PD72291 NEC uPD72291 Coprocessor 000008H PD72291 PD70236A
Text: NEC /¿PD70236A 11. |lPD72291 FLOATING-POINT CO-PROCESSOR INTERFACE The interface between the nPD72291 and the |iPD70236A is described below. 11.1 SYSTEM CONFIGURATION EXAMPLE An example of a system configuration with the nPD72291 connected to the nPD70236A is shown in Fig. 11-1.
|
OCR Scan
|
PDF
|
uPD72291
nPD72291
iPD70236A
PD70236A
nPD70236A
iPD72291
xPD72291
PD70236A.
D70236A
V53A
PD72291 NEC
Coprocessor
000008H
PD72291
PD70236A
|
D70236A
Abstract: V53A TFK 035 U 111 B tfk bb 204 U10108E TFK S 417 T NEC FIP TFK U 217 B TFK 544 PD71051
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD70236A V53A 16-BIT MICROPROCESSOR DESCR IPTIO N The |iPD70236A V53A is a 16-bit CMOS microprocessor that is software-compatible with the jiPD70136A (V33A™). The nPD70236A is based on the |xPD70236 (V53™) with the only difference being its CPU, which is equivalent to that
|
OCR Scan
|
PDF
|
uPD70236A
V53ATM
16-BIT
iPD70236A
jiPD70136A
V33ATM)
nPD70236A
xPD70236
V53TM)
D70236A
V53A
TFK 035 U 111 B
tfk bb 204
U10108E
TFK S 417 T
NEC FIP
TFK U 217 B
TFK 544
PD71051
|
D71037
Abstract: D70236A HPD71071
Text: NEC 4. ¿¿PD70236A SY STEM C O N T R O L I/O The system control l/Os which control the entire |iPD70236A are described below. In the |iPD70236A, addresses FFOOH to FFFFH are reserved as the internal I/O area, onto which system control l/Os are mapped. When using the nPD70236A these l/Os must first be correctly initialized.
|
OCR Scan
|
PDF
|
uPD70236A
PD70236A
iPD70236A,
nPD70236A
64K-byte
0000H
iPD70236A
D71037
D70236A
HPD71071
|
D70236A
Abstract: No abstract text available
Text: NEC juPD70236A 10. DMAU DMA CONTROL UNIT The DMAU has four DMA channels, and provides the functions (subsets) of two LSIs: The nPD71071 and uPD71037. 10.1 FEATURES • 2 operating modes (nPD71071 mode, |iPD71037 mode) • 24-bit length address register • 16-bit length count register
|
OCR Scan
|
PDF
|
uPD70236A
nPD71071
uPD71037
iPD71037
24-bit
16-bit
PD71037
PD71071
D70236A
|
PGR15
Abstract: JUPD70236 FF2E PGR43 nec 3114
Text: NEC 3. ¿¿PD70236A CPU The CPU has equivalent functions to the nPD70136A. In hardware terms there are some changes in the relation between on-chip peripherals and use of bus, but in software terms the two are fully compatible. The CPU internal block diagram is shown in Fig. 3-1.
|
OCR Scan
|
PDF
|
uPD70236A
nPD70136A.
16-bit
xPD72291
PGR15
JUPD70236
FF2E
PGR43
nec 3114
|
Untitled
Abstract: No abstract text available
Text: NEC /1PD70236A 5. WCU WAIT CONTROL UNIT The WCU has the function of automatically inserting a wait states(TW) equivalent to between 0 and 7 clock cycles in a CPU, DMAU or REFU bus cycle. 5.1 FEATURES • Automatic setting of 0 to 7 waits in a CPU memory bus cycle
|
OCR Scan
|
PDF
|
uPD70236A
16M-byte
PD70236A
|
NEC V33A
Abstract: NEC V20 cpu
Text: NEC /¿PD70236A 2. BLOCK CONFIGURATION 2.1 CPU The CPU has the same functions as the |iPD70136A V33A , and has an instruction set that is upward compatible with the native mode of the V20, V30, V40 and V50. The address space can be expanded to 16M bytes. 2.2 CG (CLOCK GENERATOR)
|
OCR Scan
|
PDF
|
uPD70236A
iPD70136A
16-bit
nPD71051
RS-232-C
nPD71059
iPD71071
PD71037.
NEC V33A
NEC V20 cpu
|