ARM926EJS
Abstract: ARM926EJ-S cdm-9 NAND FLASH Controller i2s1tx_clk
Text: LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 Preliminary data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high
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LPC3220/30/40/50
16/32-bit
LPC3220/30/40/50
ARM926EJ-S
LPC3220
ARM926EJS
cdm-9
NAND FLASH Controller
i2s1tx_clk
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VFP9-S
Abstract: CP15 ARM Architecture Reference Manual VFP9S 0x00000000b
Text: VFP9-S Vector Floating-point Coprocessor r0p2 Technical Reference Manual Copyright 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0238B VFP9-S r0p2 Vector Floating-point Coprocessor Technical Reference Manual Copyright © 2002, 2003 ARM Limited. All rights reserved.
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0238B
VFP9-S
CP15
ARM Architecture Reference Manual
VFP9S
0x00000000b
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MMCX decoupling TOOL
Abstract: 6691 USB connector
Text: AM3517/05 ARM Microprocessor www.ti.com SPRS550 – OCTOBER 2009 1 AM3517/05 ARM Microprocessor 1.1 Features AM3517/05 ARM Microprocessor: – Software Compatible with OMAPTM 3 Processors* – MPU Subsystem • 500-MHz ARM Cortex-A8 Core • NEON SIMD Coprocessor and Vector
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AM3517/05
SPRS550
500-MHz
16-bit
491-pin
MMCX decoupling TOOL
6691 USB connector
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1m80f
Abstract: MC9S12XHZ512 1L15Y MC9S12XDP512 simple s12x architecture 1M84E L15Y MC9S12XB128 MC9S12XDT384 MC9S12XDT512
Text: Freescale Semiconductor Application Note Investigating XGATE Software Errors XGATEV2 S12X Software Error Debugging Aid by: Dirk Heisswolf MCD Design Munich, Germany 1 Introduction The XGATE peripheral coprocessor includes a safety feature called Software Error Detection. The Software
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CPU12X
S12XE
1m80f
MC9S12XHZ512
1L15Y
MC9S12XDP512
simple s12x architecture
1M84E
L15Y
MC9S12XB128
MC9S12XDT384
MC9S12XDT512
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atmel 432
Abstract: No abstract text available
Text: AT40K05AL, AT40K10AL AT40K20AL, AT40K40AL 5K – 50K Gates Coprocessor FPGA with FreeRAM SUMMARY DATASHEET Features Ultra High Performance ̶ ̶ System Speeds to 100MHz Array Multipliers > 50MHz 10ns Flexible SRAM Internal Tri-state Capability in Each Cell
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AT40K05AL,
AT40K10AL
AT40K20AL,
AT40K40AL
100MHz
50MHz
XC4000
XC5200
atmel 432
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DSP56300
Abstract: DSP56307 DSP56311 MSC8101 SC140
Text: Order Number: AN2084/D Rev. 0, 3/2001 MOTOROLA Semiconductor Products Sector Application Note Differences Between the DSP56300 and MSC8101 Enhanced Filter Coprocessors EFCOPs By Tina M. Redheendran The Enhanced Filter Coprocessor (EFCOP) is a general-purpose,
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AN2084/D
DSP56300
MSC8101
DSP56300
DSP56307
DSP56311
SC140
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HS488
Abstract: NAT4882 TNT4882C
Text: Combination GPIB Controller/Analyzer for ISA AT-GPIB/TNT+ Features AT-GPIB/TNT+ Processor PC AT ISA , Plug and Play ISA Intel 386 or higher, math coprocessor required Overview The AT-GPIB/TNT+ combines the functionality of the AT-GPIB/TNT (Plug and Play) IEEE 488.2 Controller
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16-bit
TNT4882C
24-pin
HS488
NAT4882
TNT4882C
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INS16Cx50
Abstract: cea f23 rtc 1301 cea g22 matrix m21 ARM926EJ-S LPC3180 LPC3180FEL320 PL080 difference between arm7 and arm9
Text: LPC3180 16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface Rev. 01 — 2 June 2006 Preliminary data sheet 1. General description The LPC3180 is an ARM9-based microcontroller for embedded applications requiring
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LPC3180
16/32-bit
LPC3180
ARM926EJ-S
INS16Cx50
cea f23
rtc 1301
cea g22
matrix m21
LPC3180FEL320
PL080
difference between arm7 and arm9
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MAZ80510ML
Abstract: irf7832 AN6041 POWR1014A ZXCT1009 AN6046 zener AMC zener 1v2
Text: AMC Module Power Management April 2010 Reference Design RD1070 Introduction This reference design describes the use of a Lattice Power Manager II device as a Payload Power Management Coprocessor in an Advanced Mezzanine Card AMC system. The Advanced Mezzanine Card is intended to be
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RD1070
2N3904
RD1070
MPDTH03050WAS
MPDTH03050
MAZ80510ML
irf7832
AN6041
POWR1014A
ZXCT1009
AN6046
zener AMC
zener 1v2
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ds28el22
Abstract: No abstract text available
Text: ABRIDGED DATA SHEET DS24L65 DeepCover Secure Authenticator with SHA-256 Coprocessor and 1-Wire Master Function General Description Features DeepCover embedded security solutions cloak sensitive data under multiple layers of advanced physical security to
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DS24L65
SHA-256
32-Byte
DS24L65)
SHA256
SHA-256
com/DS24L65
ds28el22
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H1000E
Abstract: TNETA1575 TNETA1585 h1001A-1D
Text: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 D D D D D D D D D Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections Used With the TNETA1575 to Provide a
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TNETA1585
SDNS041A
TNETA1575
H1000E
TNETA1585
h1001A-1D
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ORELA 4500
Abstract: toccata WOLA adaptive reference wola WDRC WOLA reference 4500 Series
Text: AND8384/D Using Block Floating-Point in the WOLA Filterbank Coprocessor http://onsemi.com APPLICATION NOTE WOLA_Start macro, specifying the desired function as a parameter 0 for analysis, 1 for gain application and 2 for synthesis . Consequently, only a “start” macro execution is
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AND8384/D
ORELA 4500
toccata
WOLA adaptive reference
wola
WDRC
WOLA reference
4500 Series
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km3702
Abstract: KM3701 KM3702A Quadrature Encoder Zero clamp KM3702AD KM3702AD/AQ
Text: r&TOKO KM3702AD/AQ INTERPOLATION COPROCESSOR FEATURES APPLICATIONS • Interfaces Directly with an 8 Bit Microprocessor ■ Motion Control Systems ■ Wide Application Range ■ Robotics ■ Reduced Number of Counter ICs ■ Drawing Machines ■ Reduced Parts Count
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KM3702AD/AQ
KM3702AD/AQ
KM3702A
KM3701
KM3701AD
km3702
KM3702A
Quadrature Encoder
Zero clamp
KM3702AD
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8087 data types
Abstract: 8087 coprocessor instruction set 8087 coprocessor architecture bcd addition program of 8086 intel 8087 architecture coprocessor intel 8087 amd 8086 8087 architecture and configuration 8284A clock generator driver 8086 interfacing of memory devices with 8086
Text: 8087 Numeric Data Coprocessor ÌAPX86 Family DISTINCTIVE CHARACTERISTICS • • • High perform ance arithm etic and transcendental fu n c tions in hardware Supports 8-, 16-, 32-, 64-bit integer Performs 32-, 64-, 80-bit floating point calculations conforming to !EEE standard
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APX86
64-bit
80-bit
16-bit
02037B
8087 data types
8087 coprocessor instruction set
8087 coprocessor architecture
bcd addition program of 8086
intel 8087 architecture
coprocessor intel 8087
amd 8086
8087 architecture and configuration
8284A clock generator driver 8086
interfacing of memory devices with 8086
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intel 80287
Abstract: ibm at motherboard 80286 intel 80286 TECHNICAL intel 80287 arithmetic coprocessor 80C287-16 ic 80286 intel 80C287 coprocessor
Text: 80C287 Coprocessor/Software Accelerator Performance Benchmarks by Linda Bishop INTRODUCTION The math coprocessor/software accelerator performing floating-point arithmetic helps your 80286-based com puter do more work in less time. A computer with a high-speed math coprocessor installed can perform
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80C287
80286-based
BLP88,
TSA88
AST100
intel 80287
ibm at motherboard 80286
intel 80286 TECHNICAL
intel 80287 arithmetic coprocessor
80C287-16
ic 80286
intel 80C287
coprocessor
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80286based
Abstract: JC EG
Text: a AMD 80C287 Advanced Micro Devices 80-Bit CMOS Math Coprocessor DISTINCTIVE CHARACTERISTICS • High-performance CMOS process yields 10-MHz and 12-MHz speed grades ■ Available In space-saving 44-pin PLCC as well as 40-pin DIP ■ BO-blt numeric accelerator for 80C28&- and
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80C287TM
80-Bit
10-MHz
12-MHz
44-pin
40-pin
80C28
80286-based
18-diglt
80C286
80286based
JC EG
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79R3000
Abstract: No abstract text available
Text: RISC CPU PROCESSOR IDT79R3000A IDT79R3000AE Integrated Device Technology, Inc. FEATURES: Dynamically able to switch between Big- and Little- Endian byte ordering conventions. Coprocessor Interface— The IDT79R3000A generates all addresses and handles memory interface control for up to
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IDT79R3000A
IDT79R3000AE
IDT79R3000A
40MHz
MIL-STD-883,
GD175
GD144
175-Pin
144-Pin
172-Pin
79R3000
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Untitled
Abstract: No abstract text available
Text: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs
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82596CA
32-BIT
10BASE-T,
10BASE5
10BASE2
10BASE-F
82596CA
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coprocessor
Abstract: No abstract text available
Text: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily
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Intel387â
ASM286
ASM86
ASM286
ASM86.
coprocessor
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SAB-R3010
Abstract: No abstract text available
Text: il* e 23 SIEMENS High-Performance Floating-Point Coprocessor SAB-R3010A based on Advanced RISC Architecture with four Independent Arithmetic Functional Units Advance Inform ation Fully conform s to ANSI/IEEE standard 754-1985 tor binary floating-point arithmetic
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SAB-R3010A
SAB-R2010A,
SAB-R3010
64-bit
SAB-R3010A
SAB-R3000A
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Untitled
Abstract: No abstract text available
Text: intJ 80C187 80-BIT MATH COPROCESSOR • High Performance 80-Bit Internal Architecture ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic ■ Upward Object-Code Compatible from 8087 ■ Fully Compatible with 387DX and 387SX Math Coprocessors. Implements all 387
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80C187
80-BIT
387DX
387SX
80C186
80C186/80C187
80C186â
64-Bit
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m8087-2
Abstract: No abstract text available
Text: M8087 NUMERIC DATA PROCESSOR Military • High Performance Numeric Data Coprocessor ■ Standard M8086 Instruction Set Plus Arithmetic, Trigonometric, Exponential, and Logarithmic Instructions for All Data Types ■ All 24 Addressing Modes Available with M8086, M8088, M80186 CPUs
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M8087
M8086
M8086,
M8088,
M80186
64-Bit
80-Bit
18-Digit
40-Pin
m8087-2
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Untitled
Abstract: No abstract text available
Text: ü ja lile o . GT-96010 Remote Access Coprocessor Preliminary Revision 1.0 8/12/97 Please contact Galileo Technology for possi b e updates before finalizing a design. FEATURES * Integrated serial communications controller and system core logic device - Direct interface to i960 Jx family of CPUs
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GT-96010
i960Hx
128Mbyte
256K-4M
32-bit
16-bit
31CLK
ive\9601Old
GT-96010
ve\960l
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Untitled
Abstract: No abstract text available
Text: TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES • Single-Chip Scheduler for Scheduling Available Bit Rate ABR Connections • Used With the TNETA1575 to Provide a Complete Solution for Segmentation and Reassembly of Data on ABR Connections
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TNETA1585
SDNS041
TNETA1575
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